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"SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs."

Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde (2018)

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DOI: 10.1109/FPT.2018.00027

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-27

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  dblp key:
  - conf/fpt/RavishankarFG18
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  - https://dblp.org/rec/conf/fpt/RavishankarFG18
Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde:
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. FPT 2018: 118-125

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