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"Impact of guard ring layout on the stacked low-voltage PMOS for ..."

Seian-Feng Liao et al. (2015)

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DOI: 10.1109/ECCTD.2015.7300108

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - conf/ecctd/LiaoTKYCHTJL15
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  - https://dblp.org/rec/conf/ecctd/LiaoTKYCHTJL15
Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin:
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. ECCTD 2015: 1-4

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