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ORCID"A power-efficient FPGA accelerator: Systolic array with cache-coherent ..."
Megumi Ito, Moriyoshi Ohara (2016)
- Megumi Ito, Moriyoshi Ohara:
A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm. COOL Chips 2016: 1-3
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