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"A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC ..."

Kesami Hagiwara et al. (2018)

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DOI: 10.1109/COOLCHIPS.2018.8373084

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/coolchips/HagiwaraHKAENTN18
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  persistent URL:
  - https://dblp.org/rec/conf/coolchips/HagiwaraHKAENTN18
Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham:
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. COOL CHIPS 2018: 1-3

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