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"Architecture and VLSI realization of a high-speed programmable decoder for ..."

Marcos B. S. Tavares et al. (2008)

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DOI: 10.1109/ASAP.2008.4580181

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Marcos B. S. Tavares, Steffen Kunze, Emil Matús, Gerhard P. Fettweis:
Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes. ASAP 2008: 215-220

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