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ORCID"A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology."
Jyoshnavi Akiri et al. (2022)
- Jyoshnavi Akiri, Lean Karlo S. Tolentino
, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang:
A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. APCCAS 2022: 251-255
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