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"Timed Verification of Asynchronous Circuits."

Jesper B. Møller, Henrik Hulgaard, Henrik Reif Andersen (2002)

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DOI: 10.1007/3-540-36190-1_8

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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  dblp key:
  - conf/ac/MollerHA02
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  - https://dblp.org/rec/conf/ac/MollerHA02
Jesper B. Møller, Henrik Hulgaard, Henrik Reif Andersen:
Timed Verification of Asynchronous Circuits. Concurrency and Hardware Design 2002: 274-312

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