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ORCIDAndrew D. Hilton
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2010 – 2019
- 2019
[c13]Andrew D. Hilton, Genevieve M. Lipp, Susan H. Rodger:
Translation from Problem to Code in Seven Steps. CompEd 2019: 78-84- [c12]Ziqiang Huang, José A. Joao, Alejandro Rico, Andrew D. Hilton, Benjamin C. Lee:
DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management. MICRO 2019: 426-439 - [i2]Aditya Srinivasan, Andrew D. Hilton:
Gemini: A Functional Programming Language for Hardware Description. CoRR abs/1911.03926 (2019) - 2018
- [c11]Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee:
MAPS: Understanding Metadata Access Patterns in Secure Memory. ISPASS 2018: 33-43 - [c10]Andrew D. Hilton, Genevieve M. Lipp, Susan H. Rodger:
A technique for translation from problem to code. ITiCSE 2018: 375 - 2016
- [c9]Ziqiang Huang, Andrew D. Hilton, Benjamin C. Lee:
Decoupling Loads for Nano-Instruction Set Computers. ISCA 2016: 406-417 - [c8]Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee:
PoisonIvy: Safe speculation for secure memory. MICRO 2016: 38:1-38:13 - [i1]Blake A. Hechtman, Andrew D. Hilton, Daniel J. Sorin:
TREES: A CPU/GPU Task-Parallel Runtime with Explicit Epoch Synchronization. CoRR abs/1608.00571 (2016) - 2015
- [c7]Adam N. Jacobvitz, Andrew D. Hilton, Daniel J. Sorin:
Multi-program benchmark definition. ISPASS 2015: 72-82 - 2012
- [c6]Steven J. Battle, Andrew D. Hilton, Mark Hempstead, Amir Roth:
Flexible register management using reference counting. HPCA 2012: 273-284 - 2010
- [j2]Andrew D. Hilton, Amir Roth:
SMT-Directory: Efficient Load-Load Ordering for SMT. IEEE Comput. Archit. Lett. 9(1): 25-28 (2010) - [j1]Andrew D. Hilton, Santosh Nagarakatte
, Amir Roth:
iCFP: Tolerating All-Level Cache Misses in In-Order Processors. IEEE Micro 30(1): 12-19 (2010) - [c5]Andrew D. Hilton, Amir Roth:
BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution. HPCA 2010: 1-12
2000 – 2009
- 2009
- [c4]Andrew D. Hilton, Neeraj Eswaran, Amir Roth:
CPROB: Checkpoint Processing with Opportunistic Minimal Recovery. PACT 2009: 159-168 - [c3]Andrew D. Hilton, Santosh Nagarakatte, Amir Roth:
iCFP: Tolerating all-level cache misses in in-order processors. HPCA 2009: 431-442 - [c2]Andrew D. Hilton, Amir Roth:
Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors. ISCA 2009: 245-254 - 2007
- [c1]Andrew D. Hilton, Amir Roth:
Ginger: control independence using tag rewriting. ISCA 2007: 436-447
Coauthor Index
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