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ORCIDKeisuke Inoue
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2020 – today
- 2020
[c31]Keisuke Inoue, Fumihiko Sakaue, Jun Sato:
Removing Reflection from In-vehicle Camera Image. VISIGRAPP (4: VISAPP) 2020: 222-228
2010 – 2019
- 2019
- [c30]Keisuke Inoue:
An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures. VLSI-SoC 2019: 71-74 - 2018
- [c29]Keisuke Inoue, Toshiki Honda, Kohei Mukaiyama, Tetsushi Ohki, Masakatsu Nishigaki:
Automatic Examination-Based Whitelist Generation for XSS Attack Detection. BWCCA 2018: 326-338 - 2017
- [c28]Keisuke Inoue:
A dependable ASIC architecture with RT-level rollback for controller soft error recovery. NORCAS 2017: 1-4 - 2016
- [c27]Keisuke Inoue:
ECC module optimization for storage transient error-tolerant ASICs. ICECS 2016: 269-272 - 2015
- [c26]Keisuke Inoue, Mineo Kaneko:
Bitwidth-aware register allocation and binding for clock period minimization. MWSCAS 2015: 1-4 - 2014
- [c25]Keisuke Inoue, Takao Nishizeki:
Spanning Distribution Forests of Graphs - (Extended Abstract). FAW 2014: 117-127 - [c24]Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko:
An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops 2014: 251-256 - 2013
- [j12]Keisuke Inoue, Mineo Kaneko:
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(8): 1712-1722 (2013) - [j11]Keisuke Inoue, Mineo Kaneko:
Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2689-2697 (2013) - 2012
- [j10]Keisuke Inoue, Mineo Kaneko:
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2330-2337 (2012) - [c23]Keisuke Inoue, Mineo Kaneko:
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. ASP-DAC 2012: 239-244 - [c22]Keisuke Inoue, Mineo Kaneko:
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis. ACM Great Lakes Symposium on VLSI 2012: 79-82 - [c21]Keisuke Inoue, Mineo Kaneko:
Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis. ISCAS 2012: 1664-1667 - [c20]Keisuke Inoue, Mineo Kaneko:
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis. ISQED 2012: 778-783 - [c19]Keisuke Inoue, Mineo Kaneko:
Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis. MWSCAS 2012: 631-634 - 2011
- [j9]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(4): 1067-1081 (2011) - [j8]Keisuke Inoue, Mineo Kaneko:
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. Inf. Media Technol. 6(4): 1103-1115 (2011) - [j7]Keisuke Inoue, Mineo Kaneko:
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. IPSJ Trans. Syst. LSI Des. Methodol. 4: 232-244 (2011) - [c18]Mineo Kaneko, Keisuke Inoue:
Ordered coloring-based resource binding for datapaths with improved skew-adjustability. ACM Great Lakes Symposium on VLSI 2011: 307-312 - [c17]Keisuke Inoue, Mineo Kaneko:
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis. ISCAS 2011: 550-553 - [c16]Keisuke Inoue, Mineo Kaneko:
Early planning for RT-level delay insertion during clock skew-aware register binding. VLSI-SoC 2011: 154-159 - 2010
- [c15]Keisuke Inoue, Mineo Kaneko:
Optimal register assignment with minimum-delay compensation for latch-based design. APCCAS 2010: 887-890 - [c14]Keisuke Inoue, Mineo Kaneko:
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. ACM Great Lakes Symposium on VLSI 2010: 111-114
2000 – 2009
- 2009
- [j6]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1096-1105 (2009) - [c13]Keisuke Inoue:
Discourse analysis of online chat reference interviews for modeling online information-seeking dialogues. ASIST 2009: 1-15 - [c12]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI 2009: 27-32 - 2008
- [j5]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1044-1053 (2008) - [c11]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Safe clocking register assignment in datapath synthesis. ICCD 2008: 120-127 - [e1]Ebru Arisoy, Keisuke Inoue, Wolfgang Maier:
ACL 2008, Proceedings of the 46th Annual Meeting of the Association for Computational Linguistics, June 15-20, 2008, Columbus, Ohio, USA, Student Research Workshop. The Association for Computer Linguistics 2008 [contents] - 2006
- [c10]James Howison, Keisuke Inoue, Kevin Crowston
:
Social dynamics of free and open source team communications. OSS 2006: 319-330 - 2005
- [c9]Tsuyoshi Idé, Keisuke Inoue:
Knowledge Discovery from Heterogeneous Dynamic Systems using Change-Point Correlations. SDM 2005: 571-575 - 2003
- [j4]Kazuhiro Shimonomura, Keisuke Inoue, Seiji Kameda, Tetsuya Yagi:
A Novel Robot Vision Applicable to Real-time Target Tracking. J. Robotics Mechatronics 15(2): 185-191 (2003) - 2001
- [j3]Keisuke Inoue, Takayuki Itoh, Atsushi Yamada, Tomotake Furuhata, Kenji Shimada:
Face clustering of a large-scale CAD model for surface mesh generation. Comput. Aided Des. 33(3): 251-261 (2001) - [j2]Tatsuya Koyama, Keisuke Inoue, Hirokazu Hanaki, Masahiro Yasue, Eiji Iwata:
A 250-MHz single-chip multiprocessor for audio and video signal processing. IEEE J. Solid State Circuits 36(11): 1768-1774 (2001) - 2000
- [c8]Atsushi Yamada, Keisuke Inoue, Takayuki Itoh, Kenji Shimada:
An Approach for Generating Meshes Similar to A Reference Mesh. IMR 2000: 101-109
1990 – 1999
- 1999
- [c7]Masaki Wakabayashi, Keisuke Inoue, Hideharu Amano:
ISIS: Multiprocessor Simulator Library. Applied Informatics 1999: 198-200 - [c6]Keisuke Inoue, Takayuki Itoh, Atsushi Yamada, Tomotake Furuhata, Kenji Shimada:
Clustering Large Number of Faces for 2-Dimensional Mesh Generation. IMR 1999: 281-292 - 1998
- [c5]Takayuki Itoh, Kenji Shimada, Keisuke Inoue, Atsushi Yamada, Tomotake Furuhata:
Automated Conversion of 2D Triangular Mesh into Quadrilateral Mesh with Directionality Control. IMR 1998: 77-86 - 1997
- [j1]Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano:
A study on snoop cache systems for single-chip multiprocessors. Syst. Comput. Jpn. 28(2): 62-72 (1997) - [c4]Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano:
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. Euro-Par 1997: 793-797 - [c3]Toru Ohira, Keisuke Inoue, Yoshiteru Takeshima:
Traffic Control Model with Neural Network Analogy. ICONIP (2) 1997: 939-942 - 1996
- [c2]Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano:
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. FPL 1996: 200-209 - 1991
- [c1]Shuichi Shimizu, Keisuke Inoue, Masayuki Numao:
An ATMS-based geometric constraint solver for 3D CAD. ICTAI 1991: 282-290
Coauthor Index
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