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Sarang Kazeminia
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2020 – today
- 2020
- [j8]Sarang Kazeminia
, Arefeh Soltani:
A low-jitter leakage-free digitally calibrated phase locked loop. Comput. Electr. Eng. 88: 106865 (2020)
2010 – 2019
- 2019
- [j7]Sarang Kazeminia
:
A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs. Integr. 65: 51-73 (2019) - 2018
- [j6]Sarang Kazeminia
, Khayrollah Hadidi:
A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs. Integr. 61: 88-100 (2018) - 2017
- [c14]Sarang Kazeminia
, Maryam Ghafoorzadeh, Faeze Noruzpur:
An extendable global clock high-speed binary counter compatible to the FPGA CLBs. MIXDES 2017: 220-223 - 2016
- [c13]Sarang Kazeminia
, Arefeh Soltani:
Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch. APCCAS 2016: 79-82 - [c12]Sarang Kazeminia
, Arefeh Soltani:
Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs. APCCAS 2016: 680-683 - [c11]Arefeh Soltani, Roozbeh Abdollahi, Sarang Kazeminia
:
Programmable incrementing/decrementing binary accumulator for high-speed calibration loops. ICECS 2016: 636-639 - [c10]Sarang Kazeminia
, Sina Mahdavi:
A 800MS/s, 150µV input-referred offset single-stage latched comparator. MIXDES 2016: 119-123 - [c9]Sarang Kazeminia
, Sina Mahdavi, Reza Gholamnejad:
Bulk controlled offset cancellation mechanism for single-stage latched comparator. MIXDES 2016: 174-178 - [c8]Sarang Kazeminia
, Sina Mahdavi, Khayrollah Hadidi:
Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs. MIXDES 2016: 197-202 - 2015
- [j5]Sarang Kazeminia
, Sobhan Sofimowloodi
, Khayrollah Hadidi:
A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump. J. Circuits Syst. Comput. 24(1): 1550001:1-1550001:18 (2015) - [j4]Sarang Kazeminia
, Khayrollah Hadidi, Abdollah Khoei
:
A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs. J. Circuits Syst. Comput. 24(7): 1550104:1-1550104:24 (2015) - [c7]Arash Hejazi
, Sarang Kazeminia
, Roozbeh Abdollahi:
A digitally assisted 20MHz-600MHz 16-phase DLL enhanced with dynamic gain control loop. ECCTD 2015: 1-4 - 2013
- [c6]Sarang Kazeminia
, Obalit Shino, Ehsan Haghighi, Khayrollah Hadidi:
Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs. ECCTD 2013: 1-4 - 2011
- [j3]Sarang Kazeminia
, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei
:
A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process. IEICE Trans. Electron. 94-C(4): 635-640 (2011) - [c5]Sarang Kazeminia
, Khayrollah Hadidi, Abdollah Khoei
, Mohammad-Naghi Azarmanesh:
Effect of bandgap energy temperature dependence on thermal coefficient of bandgap reference voltage. ECCTD 2011: 449-452 - 2010
- [c4]Sarang Kazeminia
, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei
:
High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection. APCCAS 2010: 216-219
2000 – 2009
- 2009
- [c3]Mohammad Soleimani, Abdollah Khoei
, Khayrollah Hadidi, Sarang Kazeminia
:
Design of high-speed high-precision voltage-mode MAX-MIN circuits with low area and low power consumption. ECCTD 2009: 351-354 - 2008
- [j2]Sarang Kazeminia
, Khayrollah Hadidi, Abdollah Khoei
:
A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 491-496 (2008) - 2007
- [j1]Sarang Kazeminia
, Abdollah Khoei
, Khayrollah Hadidi:
High Speed High Precision voltage-Mode Max and Min Circuits. J. Circuits Syst. Comput. 16(2): 233-244 (2007) - [c2]Sarang Kazeminia
, Khayrollah Hadidi:
An Open Loop Phase Shifter and Frequency Synthesizer. ICECS 2007: 653-656 - 2006
- [c1]Sarang Kazeminia
, Abdollah Khoei
, Khayrollah Hadidi:
High Speed High Precision Voltage-Mode MAX and MIN Circuits. ICECS 2006: 272-275
Coauthor Index
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