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ORCIDAhmad A. Hiasat
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2020 – today
- 2022
[j24]Ahmad A. Hiasat
:
An arithmetic scaler circuit design for the expanded four-moduli set {2k-1, 2k+1, 22k+1, 22k}. Comput. Electr. Eng. 101: 108102 (2022)- 2020
- [j23]Ahmad A. Hiasat:
A Scaler Design for the RNS Three-Moduli Set {2n+1-1, 2n, 2n-1} Based on Mixed-Radix Conversion. J. Circuits Syst. Comput. 29(3): 2050041:1-2050041:12 (2020)
2010 – 2019
- 2019
- [j22]Ahmad A. Hiasat, Leonel Sousa:
On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets {2n+k, 2n - 1, 2n+1 - 1}. Comput. J. 62(2): 292-300 (2019) - [j21]Ahmad A. Hiasat:
A Residue-to-Binary Converter with an Adjustable Structure for an Extended RNS Three-Moduli Set. J. Circuits Syst. Comput. 28(8): 1950126:1-1950126:24 (2019) - [j20]Ahmad A. Hiasat, Leonel Sousa:
Sign Identifier for the Enhanced Three Moduli Set {2 n + k , 2 n - 1, 2 n+ 1 - 1}. J. Signal Process. Syst. 91(8): 953-961 (2019) - 2018
- [j19]Ahmad A. Hiasat:
New Residue Number System Scaler for the Three-Moduli Set {2n+1 - 1, 2n, 2n - 1}. Comput. 7(3): 46 (2018) - [j18]Ahmad A. Hiasat:
General modular adder designs for residue number system applications. IET Circuits Devices Syst. 12(4): 424-431 (2018) - [j17]Ahmad A. Hiasat:
Sign detector for the extended four-moduli set { 2n - 1 , 2n + 1 , 22n + 1 , 2n + k }. IET Comput. Digit. Tech. 12(2): 39-43 (2018) - 2017
- [j16]Ahmad A. Hiasat:
Efficient RNS Scalers for the Extended Three-Moduli Set (2n-1, 2n+p, 2n+1). IEEE Trans. Computers 66(7): 1253-1260 (2017) - [j15]Ahmad A. Hiasat:
A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(1): 111-121 (2017) - [j14]Ahmad A. Hiasat:
An Efficient Reverse Converter for the Three-Moduli Set ( $ 2^{n+1}-1, 2^{n}, 2^{n}-1$ ). IEEE Trans. Circuits Syst. II Express Briefs 64-II(8): 962-966 (2017) - [j13]Ahmad A. Hiasat:
A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n-1, 2n+1, 22n+1, 22n+p}. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2188-2192 (2017) - 2016
- [j12]Ahmad A. Hiasat:
A Sign Detector for a Group of Three-Moduli Sets. IEEE Trans. Computers 65(12): 3580-3590 (2016)
2000 – 2009
- 2005
- [j11]Ahmad A. Hiasat:
VLSI implementation of new arithmetic residue to binary decoders. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 153-158 (2005) - 2004
- [j10]Ahmad A. Hiasat:
A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2n - (2p [plusmn] 1)). Comput. J. 47(1): 93-102 (2004) - [j9]Omar Hasan, Ahmad A. Hiasat:
Limiter discriminator detection of narrow-band duobinary FSK in a land mobile channel. Int. J. Commun. Syst. 17(1): 85-97 (2004) - [j8]Ahmad A. Hiasat:
A Suggestion for a New RNS-Based Multiplier for a Family of Moduli. Int. J. Comput. Their Appl. 11(2): 92-97 (2004) - 2003
- [j7]Ahmad A. Hiasat, Omar Hasan:
Bit-serial architecture for rank order and stack filters. Integr. 36(1-2): 3-12 (2003) - [j6]Ahmad A. Hiasat:
An arithmetic residue to binary conversion technique. Integr. 36(1-2): 13-25 (2003) - [j5]Ahmad A. Hiasat, Andraos Sweidan:
Residue number system to binary converter for the moduli set (2n-1, 2n-1, 2n+1). J. Syst. Archit. 49(1-2): 53-58 (2003) - 2002
- [j4]Ahmad A. Hiasat:
High-Speed and Reduced-Area Modular Adder Structures for RNS. IEEE Trans. Computers 51(1): 84-89 (2002) - 2001
- [j3]Andraos Sweidan, Ahmad A. Hiasat:
On the Theory of Error Control Based on Moduli with Common Factors. Reliab. Comput. 7(3): 209-218 (2001) - [c5]Ahmad A. Hiasat:
Semi-custom VLSI chip implementation of a new two-dimensional separable median filtering algorithm. ICECS 2001: 841-844 - 2000
- [j2]Ahmad A. Hiasat:
New Efficient Structure for a Modular Multiplier for RNS. IEEE Trans. Computers 49(2): 170-174 (2000)
1990 – 1999
- 1999
- [j1]Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy:
Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm. Comput. J. 42(3): 232-240 (1999) - [c4]Ahmad A. Hiasat:
Full-custom VLSI design of a new high-speed modular adder structures. ICECS 1999: 1221-1224 - 1997
- [c3]Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy:
Design and Implementation of An RNS Division Algorithmm. IEEE Symposium on Computer Arithmetic 1997: 240-249 - 1996
- [c2]Ahmad A. Hiasat:
Semi-custom VLSI design for RNS multipliers using combinational logic approach. ICECS 1996: 935-938 - 1995
- [c1]Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy:
High-Speed Division Algorithm for Residue Number System. ISCAS 1995: 1996-1999
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