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Journal Articles
- 2021
[j1]Pierpaolo Palestri
, Ahmed Elnaqib, Davide Menin, Klaid Shyti, Francesco Brandonisio, Andrea Bandiziol, Davide Rossi, Roberto Nonis:
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1392-1401 (2021)
Conference and Workshop Papers
- 2023
- [c8]Nicolò Zugno, Francesco Brandonisio, Thomas Niederfriniger, Andrea Bevilacqua:
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies. PRIME 2023: 129-132 - 2018
- [c7]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri:
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. ISCAS 2018: 1-5 - 2016
- [c6]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri:
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers. APCCAS 2016: 321-324 - [c5]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri:
Design of a transmitter for high-speed serial interfaces in automotive micro-controller. MIPRO 2016: 84-88 - 2013
- [c4]Francesco Brandonisio, Alberto Prodomo, Michael Peter Kennedy, Ettore Napoli:
Implementation of a pulse-holding Time-to-Digital Converter on an FPGA. ECCTD 2013: 1-4 - 2011
- [c3]Francesco Brandonisio, Michael Peter Kennedy:
First order noise shaping in all digital PLLs. ISCAS 2011: 161-164 - 2010
- [c2]Francesco Brandonisio, Michael Peter Kennedy, Franco Maloberti:
First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter. ICECS 2010: 41-44 - [c1]Francesco Brandonisio, Franco Maloberti:
An all-digital PLL with a first order noise shaping Time-to-Digital Converter. ISCAS 2010: 241-244
Coauthor Index
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