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2020 – today
- 2023
[j7]Kuan-Hsun Chen, Yung-Chia Lin, Jenq-Kuen Lee:
Guest Editorial: Special Issue on Systems Optimizations for DSP and AI Applications. J. Signal Process. Syst. 95(5): 569-570 (2023)
2010 – 2019
- 2019
- [j6]Yung-Chia Lin, Jenq-Kuen Lee, François Bodin:
Guest Editorial: Special Issue on Embedded Multicore Applications and Optimization. J. Signal Process. Syst. 91(3-4): 217-218 (2019) - [c7]Chia-Hsuan Chang, Chun-Chieh Yang, Jenq-Kuen Lee, Yung-Chia Lin:
Case Study: Support OpenCL Complex Class for Baseband Computing. IWOCL 2019: 23:1-23:2
2000 – 2009
- 2009
- [j5]Chia-Han Lu, Yung-Chia Lin, Yi-Ping You
, Jenq Kuen Lee:
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. Concurr. Comput. Pract. Exp. 21(1): 101-114 (2009) - 2008
- [j4]Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee:
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch. J. Signal Process. Syst. 51(3): 257-268 (2008) - [j3]Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee:
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. J. Signal Process. Syst. 51(3): 269-288 (2008) - [c6]Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang:
An MILP-based wire spreading algorithm for PSM-aware layout modification. ASP-DAC 2008: 364-369 - 2007
- [j2]Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee:
PALF: compiler supports for irregular register files in clustered VLIW DSP processors. Concurr. Comput. Pract. Exp. 19(18): 2391-2406 (2007) - [j1]Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang:
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. J. Supercomput. 42(2): 201-223 (2007) - 2006
- [c5]Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee:
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors. RTCSA 2006: 215-222 - 2005
- [c4]Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee:
System-level design space exploration for security processor prototyping in analytical approaches. ASP-DAC 2005: 376-380 - [c3]Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee:
Compiler Supports and Optimizations for PAC VLIW DSP Processors. LCPC 2005: 466-474 - 2004
- [c2]Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang:
Power-Aware Scheduling for Parallel Security Processors with Analytical Models. LCPC 2004: 470-484 - 2002
- [c1]Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee:
Compiler Optimizations with DSP-Specific Semantic Descriptions. LCPC 2002: 75-89
Coauthor Index
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