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2020 – today
- 2023
[j1]Chenhao Huang
, Yang Ye, Yanhua Jin, Bangli Liang:
Research Progress, Hotspots, and Evolution of Nighttime Light Pollution: Analysis Based on WOS Database and Remote Sensing Data. Remote. Sens. 15(9): 2305 (2023)
2010 – 2019
- 2010
- [c8]Haizheng Guo, Bo Wang, Bangli Liang, Tad A. Kwasniewski, Robert Sobot:
Optimized LNA for analog RF front-end circuit in brain-machine interface. WCNIS 2010: 147-150
2000 – 2009
- 2009
- [c7]Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski:
A full-rate truly monolithic CMOS CDR for low-cost applications. CCECE 2009: 1208-1212 - [c6]Dianyong Chen, Bo Wang, Bangli Liang, Tad A. Kwasniewski:
A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously. CCECE 2009: 1213-1216 - [c5]Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tad A. Kwasniewski:
A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. CCECE 2009: 1221-1226 - [c4]Bangli Liang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski, Zhigong Wang:
A monolithic high modulation efficiency CMOS laser diode / modulator driver. ICT 2009: 361-363 - [c3]Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tadeusz Kwasniewski:
Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel. UKSim 2009: 574-578 - [c2]Dianyong Chen, Bo Wang, Bangli Liang, Tadeusz Kwasniewski:
A Simulator for High-Speed Backplane Transceivers. UKSim 2009: 589-593 - 2008
- [c1]Bangli Liang, Tad A. Kwasniewski, Dianyong Chen:
A 42-Gb/s Decision Circuit in 0.13µm CMOS. CNSR 2008: 339-342
Coauthor Index
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