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Journal Articles
- 2008
[j3]Ahmad Darabiha, Anthony Chan Carusone
, Frank R. Kschischang:
Power Reduction Techniques for LDPC Decoders. IEEE J. Solid State Circuits 43(8): 1835-1845 (2008)- [j2]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 74-78 (2008) - 2006
- [j1]Ahmad Darabiha, W. James MacLean, Jonathan Rose:
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm. Mach. Vis. Appl. 17(2): 116-132 (2006)
Conference and Workshop Papers
- 2007
- [c6]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. CICC 2007: 459-462 - 2006
- [c5]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
A bit-serial approximate min-sum LDPC decoder and FPGA implementation. ISCAS 2006 - 2005
- [c4]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity. ISCAS (5) 2005: 5194-5197 - 2004
- [c3]Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow:
Reconfigurable Molecular Dynamics Simulator. FCCM 2004: 197-206 - [c2]Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow:
FPGA-based supercomputing: an implementation for molecular dynamics. FPGA 2004: 253 - 2003
- [c1]Ahmad Darabiha, Jonathan Rose, W. James MacLean:
Video-Rate Stereo Depth Measurement on Programmable Hardware. CVPR (1) 2003: 203-210
Coauthor Index
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