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"A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in ..."

Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang (2007)

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DOI: 10.1109/CICC.2007.4405773

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

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Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. CICC 2007: 459-462

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