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Atsushi Kamo
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2000 – 2009
- 2005
- [c8]Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. ISCAS (5) 2005: 4903-4906 - 2004
- [c7]Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. DATE 2004: 1327-1333 - 2002
- [j2]Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai:
A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 395-398 (2002) - [j1]Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1214-1219 (2002) - [c6]I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. ISCAS (5) 2002: 29-32 - [c5]Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) 2002: 649-552 - 2001
- [c4]Masaya Suzuki, Hirofumi Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
High-speed interconnect simulation using MIMO type of adaptive least square method. ISCAS (5) 2001: 327-330 - [c3]Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Simulation for the optimal placement of decoupling capacitors on printed circuit board. ISCAS (3) 2001: 727-730
1990 – 1999
- 1999
- [c2]Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Expanded GMC for transient analysis of transmission line networks. ISCAS (6) 1999: 33-36 - 1998
- [c1]Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai:
Neural network simulator for spatiotemporal pattern analysis. ICECS 1998: 109-112
Coauthor Index
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