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ORCIDWeiwei Chen 0001
Person information
- affiliation (PhD 2013): University of California, Irvine, Center for Embedded Computer Systems, CA, USA
Other persons with the same name
- Weiwei Chen — disambiguation page
- Weiwei Chen 0002 — University of Southern California, Information Sciences Institute, Marina del Rey, CA, USA
- Weiwei Chen 0003
![[0000-0002-7736-3411]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-7736-3411")
— Rutgers University, Department of Supply Chain Management, New Brunswick, NJ, USA (and 2 more) - Weiwei Chen 0004 — Hunan University, College of Computer Science and Electronic Engineering, China (and 1 more)
- Weiwei Chen 0005 — Hong Kong University of Science and Technology, Department of Civil and Environmental Engineering
- Weiwei Chen 0006 — Sun Yat-sen University, Guangzhou, China
- Weiwei Chen 0007 — Shanghai University, Shanghai, China
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Journal Articles
- 2014
[j3]Weiwei Chen, Xu Han, Che-Wei Chang, Guantao Liu, Rainer Dömer:
Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1859-1872 (2014)- 2013
- [j2]Weiwei Chen, Xu Han, Che-Wei Chang, Rainer Dömer:
Advances in Parallel Discrete Event Simulation for Electronic System-Level Design. IEEE Des. Test 30(1): 45-54 (2013) - 2011
- [j1]Weiwei Chen, Xu Han, Rainer Dömer:
Multicore Simulation of Transaction-Level Models Using the SoC Environment. IEEE Des. Test Comput. 28(3): 20-31 (2011)
Conference and Workshop Papers
- 2014
- [c11]Weiwei Chen, Xu Han, Rainer Dömer:
May-happen-in-parallel analysis based on segment graphs for safe ESL models. DATE 2014: 1-6 - 2013
- [c10]Weiwei Chen, Rainer Dömer:
Optimized out-of-order parallel discrete event simulation using predictions. DATE 2013: 3-8 - [c9]Xu Han, Weiwei Chen, Rainer Dömer:
Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis. M-SCOPES 2013: 40-47 - 2012
- [c8]Rainer Dömer, Weiwei Chen, Xu Han:
Parallel discrete event simulation of Transaction Level Models. ASP-DAC 2012: 227-231 - [c7]Weiwei Chen, Rainer Dömer:
An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation. ASP-DAC 2012: 461-466 - [c6]Weiwei Chen, Xu Han, Rainer Dömer:
Out-of-order parallel simulation for ESL design. DATE 2012: 141-146 - [c5]Weiwei Chen, Che-Wei Chang, Xu Han, Rainer Dömer:
Eliminating race conditions in system-level models by using parallel simulation infrastructure. HLDVT 2012: 118-123 - 2011
- [c4]Rainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer:
Multi-core parallel simulation of System-level Description Languages. ASP-DAC 2011: 311-316 - 2010
- [c3]Weiwei Chen, Rainer Dömer:
A fast heuristic scheduling algorithm for periodic ConcurrenC models. ASP-DAC 2010: 161-166 - [c2]Weiwei Chen, Xu Han, Rainer Dömer:
ESL design and multi-core validation using the System-on-Chip Environment. HLDVT 2010: 142-147 - 2009
- [c1]Weiwei Chen, Rainer Dömer:
ConcurrenC: A New Approach towards Effective Abstraction of C-Based SLDLs. IESS 2009: 57-65
Coauthor Index
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