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ORCIDSomayyeh Rahimian Omam
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Journal Articles
- 2013
[j3]Somayyeh Rahimian, Vasilis F. Pavlidis, Xifan Tang, Giovanni De Micheli
:
An Enhanced Design Methodology for Resonant Clock Trees. J. Low Power Electron. 9(2): 198-206 (2013)- 2012
- [j2]Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli:
Inter-Plane Communication Methods for 3-D ICs. J. Low Power Electron. 8(2): 170-181 (2012) - 2006
- [j1]Somayyeh Rahimian Omam, Seid Mehdi Fakhraie, Omid Shoaei:
Minimizing the adder cost in multiple constant multipliers. IEICE Electron. Express 3(14): 340-346 (2006)
Conference and Workshop Papers
- 2015
- [c8]Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
A ultra-low-power FPGA based on monolithically integrated RRAMs. DATE 2015: 1203-1208 - [c7]Somayyeh Rahimian Omam, Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A study on buffer distribution for RRAM-based FPGA routing structures. LASCAS 2015: 1-4 - 2014
- [c6]Somayyeh Rahimian Omam, Yusuf Leblebici, Giovanni De Micheli:
Parallel vs. serial inter-plane communication using TSVs. LASCAS 2014: 1-5 - 2011
- [c5]Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli:
Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits. PATMOS 2011: 267-277 - 2006
- [c4]S. M. Mortazavi Zanjani, Somayyeh Rahimian Omam, Seid Mehdi Fakhraie, Omid Shoaei:
Experimental Evaluation of Different Realizations of Recursive CIC Filters. CCECE 2006: 1056-1059 - [c3]Hamed Aminzadeh, Reza Lotfi, Somayyeh Rahimian:
Design Guidelines for Two-Stage Cascode-Compensated Operational Amplifiers. ICECS 2006: 264-267 - [c2]Somayyeh Rahimian Omam, S. M. Mortazavi Zanjani, Sied Mehdi Fakhraie, Omid Shoaei:
Implementation of Multiplier Block with Reduced Adder Cost. ICECS 2006: 842-845 - [c1]Navid Zeraatkar, Ali Tavanaie, Reza Talebian, Somayyeh Rahimian:
Implementation and Synthesis of a Sorting Network. ICECS 2006: 1109-1112
Coauthor Index
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