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ORCIDYohei Hori
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2020 – today
- 2024
[j9]Hiroshi Fuketa
, Toshihiro Katashita, Yohei Hori, Masakazu Hioki:
Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. IEEE Access 12: 102470-102480 (2024)- [c20]Tatsuya Oyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino:
FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. ACNS Workshops (1) 2024: 65-83 - 2021
- [j8]Yusuke Yano, Kengo Iokibe, Toshiaki Teshima, Yoshitaka Toyota, Toshihiro Katashita, Yohei Hori:
Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices. IEICE Trans. Commun. 104-B(2): 178-186 (2021) - 2020
- [j7]Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike:
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. Integr. 71: 144-153 (2020) - [c19]Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino:
Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. ISCAS 2020: 1-5 - [i1]Mitsuru Shiozaki, Yohei Hori, Takeshi Fujino:
Entropy Estimation of Physically Unclonable Functions. IACR Cryptol. ePrint Arch. 2020: 1284 (2020)
2010 – 2019
- 2019
- [c18]Kuniyasu Suzaki, Yohei Hori, Kazukuni Kobara, Mohammad Mannan:
DeviceVeil: Robust Authentication for Individual USB Devices Using Physical Unclonable Functions. DSN 2019: 302-314 - [c17]Risa Yashiro, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama:
A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme. SECITC 2019: 78-94 - 2018
- [j6]Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike:
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. IEICE Trans. Inf. Syst. 101-D(2): 303-313 (2018) - [c16]Nicolas Bruneau, Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Soshi Hamaguchi, Yohei Hori, Yousung Kang, Alexander Schaub:
Development of the Unified Security Requirements of PUFs During the Standardization Process. SecITC 2018: 314-330 - 2017
- [c15]Toshihiro Katashita, Yohei Hori, Yasuhiro Ogasahara:
Prototype of USB stick-sized PUF module for authentication and key generation. GCCE 2017: 1-2 - 2016
- [c14]Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike:
Implementation of pseudo linear feedback shift register physical unclonable function on silicon. ISCAS 2016: 758-761 - 2015
- [c13]Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike:
Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests. GCCE 2015: 550-551 - 2014
- [j5]Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger:
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. 97-C(4): 272-279 (2014) - [j4]Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara:
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. J. Inf. Process. 22(2): 344-356 (2014) - 2013
- [j3]Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh:
Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. IEICE Trans. Inf. Syst. 96-D(11): 2333-2343 (2013) - [j2]Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata:
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2533-2541 (2013) - [c12]Toshihiro Katashita, Akihiko Sasaki, Yohei Hori:
A novel smart card development platform for evaluating physical attacks and PUFs. GCCE 2013: 37-39 - [c11]Yohei Hori, Toshihiro Katashita, Kazukuni Kobara:
Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA. GCCE 2013: 217-218 - 2011
- [c10]Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh:
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST 2011: 87-92 - [c9]Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh:
Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. ReConFig 2011: 223-228 - 2010
- [c8]Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh:
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. ReConFig 2010: 298-303
2000 – 2009
- 2008
- [j1]Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, Kenji Toda:
A Secure Content Delivery System Based on a Partially Reconfigurable FPGA. IEICE Trans. Inf. Syst. 91-D(5): 1398-1407 (2008) - [c7]Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda:
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. FPL 2008: 23-28 - [c6]Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda:
Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. IWSEC 2008: 261-278 - 2007
- [c5]Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, Kenji Toda:
A Secure Digital Content Delivery System Based on Partially Reconfigurable Hardware. FPT 2007: 253-256 - 2006
- [c4]Yohei Hori, Hiroyuki Yokoyama, Kenji Toda:
Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration. FPL 2006: 1-4 - 2004
- [c3]Yohei Hori, Tsutomu Maruyama, Kenji Toda:
A tsume-shogi processor based on reconfigurable hardware. FPT 2004: 347-350 - 2002
- [c2]Yohei Hori, Masashi Sonoyama, Tsutomu Maruyama:
An FPGA-based processor for shogi mating problems. FPT 2002: 117-124 - 2000
- [c1]Yohei Hori, Minenobu Seki, Reijer Grimbergen, Tsutomu Maruyama, Tsutomu Hoshino:
A Shogi Processor with a Field Programmable Gate Array. Computers and Games 2000: 297-314
Coauthor Index
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