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ORCIDJoshua L. Kihm
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2000 – 2009
- 2007
[c7]Joshua L. Kihm, Samuel D. Strom, Daniel A. Connors:
Phase-Guided Small-Sample Simulation. ISPASS 2007: 84-93- 2005
- [j1]Joshua L. Kihm, Alex Settle, Andrew Janiszewski, Dan Connors:
Understanding the Impact of Inter-Thread Cache Interference on ILP in Modern SMT Processors. J. Instr. Level Parallelism 7 (2005) - [c6]Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Matthew Iyer, Dan Fay, David Hodgdon, Joshua L. Kihm, Alex Settle, Dirk Grunwald, Daniel A. Connors:
Dynamic run-time architecture techniques for enabling continuous optimization. Conf. Computing Frontiers 2005: 211-220 - [c5]Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Daniel A. Connors:
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors. ICCD 2005: 373-380 - [c4]Joshua L. Kihm, Daniel A. Connors:
Statistical Simulation of Multithreaded Architectures. MASCOTS 2005: 67-74 - 2004
- [c3]Alex Settle, Joshua L. Kihm, Andrew Janiszewski, Daniel A. Connors:
Architectural Support for Enhanced SMT Job Scheduling. IEEE PACT 2004: 63-73 - [c2]Joshua L. Kihm, Andrew Janiszewski, Daniel A. Connors:
Predictable Fine-Grained Cache Behavior for Enhanced Simultaneous Multithreading (SMT) Scheduling. CCCT (1) 2004: 405-409 - [c1]Joshua L. Kihm, Daniel A. Connors:
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling. ICCD 2004: 326-331
Coauthor Index
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