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ORCIDFumihiko Tachibana
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Journal Articles
- 2024
[j5]Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi:
A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(5): 709-718 (2024)- 2020
- [j4]Asuka Maki, Daisuke Miyashita, Shinichi Sasaki, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi, Ryuichi Fujimoto:
Weight Compression MAC Accelerator for Effective Inference of Deep Learning. IEICE Trans. Electron. 103-C(10): 514-523 (2020) - 2019
- [j3]Yuta Tsubouchi
, Daisuke Miyashita, Takashi Toi, Yuji Satoh, Fumihiko Tachibana, Junji Wadatsumi, Makoto Morimoto, Ryuichi Fujimoto, Jun Deguchi:
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. IEEE J. Solid State Circuits 54(4): 1086-1095 (2019) - 2014
- [j2]Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa:
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. IEEE J. Solid State Circuits 49(1): 118-126 (2014) - 2011
- [j1]Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe:
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. IEEE J. Solid State Circuits 46(11): 2545-2551 (2011)
Conference and Workshop Papers
- 2022
- [c12]Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi:
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. ESSCIRC 2022: 505-508 - 2021
- [c11]Kengo Nakata, Daisuke Miyashita, Asuka Maki, Fumihiko Tachibana, Shinichi Sasaki, Jun Deguchi, Ryuichi Fujimoto:
Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN. AICAS 2021: 1-4 - 2019
- [c10]Kengo Nakata, Asuka Maki, Daisuke Miyashita, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi:
Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision. ISCAS 2019: 1 - 2018
- [c9]Asuka Maki, Daisuke Miyashita, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi:
FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision. A-SSCC 2018: 47-50 - [c8]Yuta Tsubouchi, Daisuke Miyashita, Yuji Satoh, Takashi Toi, Fumihiko Tachibana, Makoto Morimoto, Junji Wadatsumi, Jun Deguchi:
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems. VLSI Circuits 2018: 149-150 - 2013
- [c7]Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa:
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. ISSCC 2013: 320-321 - [c6]Jun Deguchi, Fumihiko Tachibana, Makoto Morimoto, Masayoshi Chiba, Takeshi Miyaba, Hideki Tanaka, Kyoichi Takenaka, Satoshi Funayama, Kunihiko Amano, Kazuhide Sugiura, Ryuta Okamoto, Shouhei Kousai:
A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC. ISSCC 2013: 494-495 - 2012
- [c5]Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe:
Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. ICICDT 2012: 1-4 - [c4]Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe:
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. VLSIC 2012: 100-101 - 2011
- [c3]Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe:
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. A-SSCC 2011: 161-164 - 2008
- [c2]Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada:
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. CICC 2008: 29-32 - [c1]Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi:
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. ISSCC 2008: 262-263
Coauthor Index
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