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Oscar Ruano
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2020 – today
- 2024
- [j13]José Luis Imaña, Luis Piñuel, Yao-Ming Kuo
, Oscar Ruano
, Francisco Garcia-Herrero
:
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3915-3919 (2024) - 2023
- [j12]Yao-Ming Kuo
, Mark F. Flanagan
, Francisco Garcia-Herrero
, Oscar Ruano
, Juan Antonio Maestro
:
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. IEEE Trans. Aerosp. Electron. Syst. 59(5): 5835-5846 (2023) - [j11]Yao-Ming Kuo
, Francisco Garcia-Herrero
, Oscar Ruano
, Juan Antonio Maestro
:
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. IEEE Trans. Computers 72(3): 682-692 (2023) - 2022
- [j10]Yao-Ming Kuo
, Francisco Garcia-Herrero, Oscar Ruano
, Juan Antonio Maestro:
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. Comput. Electr. Eng. 99: 107759 (2022) - [j9]Luis Alberto Aranda
, Oscar Ruano
, Francisco Garcia-Herrero
, Juan Antonio Maestro
:
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1577-1581 (2022) - [j8]Jefferson Andres Bravo-Montes, Alonso Martín-Toledano, Alfonso Sánchez-Macián
, Oscar Ruano
, Francisco Garcia-Herrero
:
Design and implementation of efficient QCA full-adders using fault-tolerant majority gates. J. Supercomput. 78(6): 8056-8080 (2022) - 2021
- [j7]Luis Alberto Aranda
, Oscar Ruano
, Francisco Garcia-Herrero
, Juan Antonio Maestro
:
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. IEEE Access 9: 140676-140685 (2021) - [j6]Oscar Ruano
, Francisco Garcia-Herrero
, Luis Alberto Aranda
, Alfonso Sánchez-Macián
, Laura Rodriguez
, Juan Antonio Maestro
:
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors 21(4): 1392 (2021)
2010 – 2019
- 2013
- [j5]Pedro Reviriego
, Oscar Ruano
, Mark F. Flanagan
, Salvatore Pontarelli
, Juan Antonio Maestro
:
An Efficient Technique to Protect Serial Shift Registers Against Soft Errors. IEEE Trans. Circuits Syst. II Express Briefs 60-II(8): 512-516 (2013) - 2012
- [j4]Pedro Reviriego
, Oscar Ruano
, Juan Antonio Maestro
:
Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters. IEEE Trans. Circuits Syst. II Express Briefs 59-II(9): 583-586 (2012) - 2011
- [j3]Oscar Ruano
, Juan Antonio Maestro
, Pedro Reviriego:
A fast and efficient technique to apply Selective TMR through optimization. Microelectron. Reliab. 51(12): 2388-2401 (2011) - [c2]Oscar Ruano
, Juan Antonio Maestro
, Pedro Reviriego:
Validation and optimization of TMR protections for circuits in radiation environments. DDECS 2011: 399-400
2000 – 2009
- 2009
- [j2]Juan Antonio Maestro
, Pedro Reviriego, Pilar Reyes, Oscar Ruano
:
Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study. Integr. 42(2): 128-136 (2009) - 2008
- [j1]Pilar Reyes, Pedro Reviriego, Juan Antonio Maestro
, Oscar Ruano
:
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study. J. Signal Process. Syst. 52(3): 231-247 (2008) - 2007
- [c1]Oscar Ruano
, Pilar Reyes, Juan Antonio Maestro
, Luca Sterpone
, Pedro Reviriego:
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. DDECS 2007: 261-266
Coauthor Index
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last updated on 2024-08-23 19:23 CEST by the dblp team
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