"Efficient Low-Latency Multiplication Architecture for NIST Trinomials With ..."

José Luis Imaña et al. (2024)

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DOI: 10.1109/TCSII.2024.3369103

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type: Journal Article

metadata version: 2024-09-08

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José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero:
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3915-3919 (2024)

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