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Nils Przigoda
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2020 – today
- 2023
- [c23]Domenik Eichhorn, Tobias Pett, Nils Przigoda, Jessica Kindsvater, Christoph Seidl, Ina Schaefer:
Coverage-Driven Test Automation for Highly-Configurable Railway Systems. VaMoS 2023: 23-30 - [i1]Stefan Engels, Tom Peham, Judith Przigoda, Nils Przigoda, Robert Wille:
Design Tasks and Their Complexity for Hybrid Level 3 of the European Train Control System. CoRR abs/2308.02572 (2023) - 2022
- [c22]Tom Peham, Judith Przigoda, Nils Przigoda, Robert Wille:
Optimal Railway Routing Using Virtual Subsections. RSSRail 2022: 63-79 - 2021
- [c21]Robert Wille, Tom Peham, Judith Przigoda, Nils Przigoda:
Towards Automatic Design and Verification for Level 3 of the European Train Control System. DATE 2021: 974-979
2010 – 2019
- 2019
- [c20]Nils Przigoda, Judith Przigoda, Robert Wille:
Four-Valued Logic in UML/OCL Models: A "Playground" for the MVL Community. ISMVL 2019: 61-66 - 2018
- [b2]Nils Przigoda, Robert Wille, Judith Przigoda, Rolf Drechsler:
Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers. Springer 2018, ISBN 978-3-319-72813-1 - [j5]Nils Przigoda, Philipp Niemann, Jonas Gomes Filho, Robert Wille, Rolf Drechsler:
Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of modifies only statements. Comput. Lang. Syst. Struct. 54: 512-527 (2018) - [c19]Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler:
Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence. MODELSWARD 2018: 139-151 - [c18]Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler:
Generation and Validation of Frame Conditions in Formal Models. MODELSWARD (Revised Selected Papers) 2018: 259-283 - 2017
- [b1]Nils Przigoda:
SMT-based validation & verification of UML-OCL models. University of Bremen, Germany, 2017, pp. 1-255 - [j4]Pablo González de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sánchez Espeso:
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 475-488 (2017) - [c17]Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler:
More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models. MEMOCODE 2017: 77-86 - 2016
- [j3]Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler:
Verifying the structure and behavior in UML/OCL models using satisfiability solvers. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 49-59 (2016) - [j2]Nils Przigoda, Robert Wille, Rolf Drechsler:
Analyzing Inconsistencies in UML/OCL Models. J. Circuits Syst. Comput. 25(3): 1640021:1-1640021:21 (2016) - [c16]Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler:
Towards a model-based verification methodology for Complex Swarm Systems (Invited paper). ISED 2016: 18-23 - [c15]Nils Przigoda, Gerhard W. Dueck, Robert Wille, Rolf Drechsler:
Fault Detection in Parity Preserving Reversible Circuits. ISMVL 2016: 44-49 - [c14]Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler:
Frame conditions in symbolic representations of UML/OCL models. MEMOCODE 2016: 65-70 - [c13]Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler:
Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. MEMOCODE 2016: 78-84 - [c12]Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler:
Integrating an SMT-Based ModelFinder into USE. MoDeVVa@MoDELS 2016: 40-45 - [c11]Nils Przigoda, Robert Wille, Rolf Drechsler:
Ground setting properties for an efficient translation of OCL in SMT-based model finding. MoDELS 2016: 261-271 - 2015
- [c10]Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler:
A generic representation of CCSL time constraints for UML/MARTE models. DAC 2015: 122:1-122:6 - [c9]Nils Przigoda, Robert Wille, Rolf Drechsler:
Contradiction Analysis for Inconsistent Formal Models. DDECS 2015: 171-176 - [c8]Nils Przigoda, Robert Wille, Rolf Drechsler:
Leveraging the Analysis for Invariant Independence in Formal System Models. DSD 2015: 359-366 - [c7]Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler:
Verification-Driven Design Across Abstraction Levels: A Case Study. DSD 2015: 375-382 - [c6]Nils Przigoda, Robert Wille, Rolf Drechsler:
Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung). MBMV 2015: 165-172 - [c5]Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler:
Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. MoDeVVa@MoDELS 2015: 44-47 - [c4]Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler:
Checking concurrent behavior in UML/OCL models. MoDELS 2015: 176-185 - 2013
- [j1]Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler:
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. J. Multiple Valued Log. Soft Comput. 21(5-6): 627-640 (2013) - [c3]Robert Wille, Nils Przigoda, Rolf Drechsler:
A compact and efficient SAT encoding for quantum circuits. AFRICON 2013: 1-6 - 2012
- [c2]Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler:
Synthesis of reversible circuits with minimal lines for large functions. ASP-DAC 2012: 85-92 - [c1]Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler:
Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. ISMVL 2012: 69-74
Coauthor Index
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