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Conference and Workshop Papers

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1998
[c5]
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  - conf/aspdac/BinhIT98
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Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi:
A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. ASP-DAC 1998: 367-372
1996
[c4]
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Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. DAC 1996: 527-532
[c3]
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Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi:
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. EURO-DAC 1996: 126-131
1995
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Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
A hardware/software codesign method for pipelined instruction set processor using adaptive database. ASP-DAC 1995
[c1]
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Nguyen-Ngoc Bình, Masaharu Imai, Nobuyuki Hikichi:
A hardware/software partitioning algorithm for pipelined instruction set processor. EURO-DAC 1995: 176-181

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