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2010 – 2019
- 2018
[c7]Koji Yamazaki, Yuta Ukon, Shuhei Yoshida, Saki Hatta, Yusuke Sekihara, Shoko Ohteru, Tomoaki Kawamura, Takahiro Hatano, Koyo Nitta
, Akihiko Miyazaki:
Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane. HPSR 2018: 1-6- 2016
- [c6]Kenta Shimazaki, Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki, Toshitaka Tsuda, Nozomu Togawa:
Hash-table and balanced-tree based FIB architecture for CCN routers. ISOCC 2016: 67-68 - 2015
- [j1]Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. IEICE Trans. Electron. 98-C(1): 45-52 (2015) - [c5]Yutaro Ishigaki, Ning Li, Yoichi Tomioka, Akihiko Miyazaki, Hitoshi Kitazawa:
An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only). FPGA 2015: 266 - [c4]Koji Yamazaki, Yoshihiro Nakajima, Takahiro Hatano, Akihiko Miyazaki:
Lagopus FPGA - A reprogrammable data plane for high-performance software SDN switches. Hot Chips Symposium 2015: 1 - 2014
- [c3]Koji Yamazaki, Takeshi Osaka, Sadayuki Yasuda, Shoko Ohteru, Akihiko Miyazaki:
Accelerating SDN/NFV with Transparent Offloading Architecture. ONS 2014 - 2012
- [c2]Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs. ISCAS 2012: 1464-1467 - 2011
- [c1]Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Akihiko Miyazaki, Masami Urano, Tsugumichi Shibata:
Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction. GLOBECOM 2011: 1-5
Coauthor Index
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