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Yago Torroja
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2000 – 2009
- 2008
- [j2]Felipe Machado
, Yago Torroja
, Teresa Riesgo:
A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation. J. Low Power Electron. 4(3): 247-262 (2008) - [c5]Felipe Machado
, Teresa Riesgo, Yago Torroja
:
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. PATMOS 2008: 399-408 - 2006
- [c4]Felipe Machado
, Teresa Riesgo, Yago Torroja
:
A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. PATMOS 2006: 645-657 - 2005
- [c3]Felipe Machado
, Teresa Riesgo, Yago Torroja
:
Switching activity propagation of VHDL-RTL combinational designs through an automated tool. ICECS 2005: 1-4
1990 – 1999
- 1999
- [j1]Teresa Riesgo, Yago Torroja
, Eduardo de la Torre:
Design methodologies based on hardware description languages. IEEE Trans. Ind. Electron. 46(1): 3-12 (1999) - 1998
- [c2]Teresa Riesgo, Yago Torroja
, Eduardo de la Torre, Javier Uceda
:
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. DATE 1998: 955-956 - 1996
- [c1]José Luis Ruiz, Yago Torroja
, José Luis García:
Design of a VME Parametrized Library for FPGAs. FPL 1996: 394-399
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