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ORCIDAlexandru Plesco
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- affiliation: ENS Lyon, France
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2020 – today
- 2021
[c6]Christophe Alias
, Alexandru Plesco:
Data-aware process networks. CC 2021: 1-11
2010 – 2019
- 2017
- [j2]Christophe Alias, Alexandru Plesco:
Optimizing Affine Control With Semantic Factorizations. ACM Trans. Archit. Code Optim. 14(4): 52:1-52:22 (2017) - 2013
- [c5]Christophe Alias, Alain Darte, Alexandru Plesco:
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA. DATE 2013: 575-580 - 2012
- [j1]Christophe Alias, Bogdan Pasca, Alexandru Plesco:
FPGA-specific synthesis of loop-nests with pipelined computational cores. Microprocess. Microsystems 36(8): 606-619 (2012) - [c4]Christophe Alias, Alain Darte, Alexandru Plesco:
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA. PPoPP 2012: 285-286 - 2011
- [c3]Christophe Alias, Bogdan Pasca, Alexandru Plesco:
Automatic Generation of FPGA-Specific Pipelined Accelerators. ARC 2011: 53-66 - [c2]Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco:
An FPGA architecture for solving the Table Maker's Dilemma. ASAP 2011: 187-194 - 2010
- [b1]Alexandru Plesco:
Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators. (Transformations de programmes et optimisations de l'architecture mémoire pour la synthèse de haut niveau d'accélérateurs matériels). École normale supérieure de Lyon, France, 2010 - [c1]Christophe Alias, Alain Darte, Alexandru Plesco:
Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool. ASAP 2010: 329-332
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