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2020 – today
- 2022
[j3]Rakesh Kumar
, Mehdi Alipour, David Black-Schaffer:
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores. ACM Trans. Archit. Code Optim. 19(2): 25:1-25:28 (2022)- [i5]Rakesh Kumar, Mehdi Alipour, David Black-Schaffer:
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores. CoRR abs/2201.00485 (2022) - 2020
- [b1]Mehdi Alipour:
Rethinking Dynamic Instruction Scheduling and Retirement for Efficient Microarchitectures. Uppsala University, Sweden, 2020 - [c11]Mehdi Alipour, Stefanos Kaxiras, David Black-Schaffer, Rakesh Kumar:
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. HPCA 2020: 424-434
2010 – 2019
- 2019
- [j2]Mehdi Alipour, Trevor E. Carlson, David Black-Schaffer, Stefanos Kaxiras:
Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit. J. Signal Process. Syst. 91(3-4): 379-397 (2019) - [c10]Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander:
Ghost loads: what is the cost of invisible speculation? CF 2019: 153-163 - [c9]Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer:
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. DATE 2019: 716-721 - [c8]Rakesh Kumar, Mehdi Alipour, David Black-Schaffer:
Freeway: Maximizing MLP for Slice-Out-of-Order Execution. HPCA 2019: 558-569 - 2018
- [j1]Stefanos Kaxiras, Trevor E. Carlson, Mehdi Alipour, Alberto Ros:
Non-Speculative Load Reordering in Total Store Ordering. IEEE Micro 38(3): 48-57 (2018) - [c7]Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind:
Constructing a Weak Memory Model. ISCA 2018: 124-137 - [i4]Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind:
Constructing a Weak Memory Model. CoRR abs/1805.07886 (2018) - 2017
- [c6]Mehdi Alipour, Trevor E. Carlson, Stefanos Kaxiras:
Exploring the Performance Limits of Out-of-order Commit. Conf. Computing Frontiers 2017: 211-220 - [c5]Alberto Ros, Trevor E. Carlson, Mehdi Alipour, Stefanos Kaxiras:
Non-Speculative Load-Load Reordering in TSO. ISCA 2017: 187-200 - [c4]Mehdi Alipour, Trevor E. Carlson, Stefanos Kaxiras:
A taxonomy of out-of-order instruction commit. ISPASS 2017: 135-136 - 2012
- [c3]Mehdi Alipour, Hojjat Taghdisi, Seyed Hassan Sadeghzadeh:
Multi objective design space exploration of cache for embedded applications. CCECE 2012: 1-4 - [i3]Mehdi Alipour, Hojjat Taghdisi:
Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications. CoRR abs/1204.2772 (2012) - [i2]Mehdi Alipour, Mostafa E. Salehi:
Performance-Optimum Superscalar Architecture for Embedded Applications. CoRR abs/1204.2809 (2012) - [i1]Mehdi Alipour, Mostafa E. Salehi, Hesamodin Shojaei Baghini:
Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications. CoRR abs/1205.1871 (2012) - 2011
- [c2]Mehdi Alipour, Mohammad Haji Seyed Javadi, Ali Jahanian:
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology. ACM Great Lakes Symposium on VLSI 2011: 49-54 - [c1]Mehdi Alipour, Kamran Moshari, Mohammad Reza Bagheri:
Performance per power optimum cache architecture for embedded applications, a design space exploration. NESEA 2011: 1-6
Coauthor Index
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