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ORCIDYuan Zhou 0011
Person information
- affiliation: University of Texas at Dallas, Department of Electrical and Computer Engineering, Richardson, TX, USA
Other persons with the same name
- Yuan Zhou — disambiguation page
- Yuan Zhou 0001
![[0000-0002-9198-6586]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-9198-6586")
— Tsinghua University, School of Public Policy and Management, Beijing, China - Yuan Zhou 0002 — University of California Davis, Department of Electrical and Computer Engineering, Davis, CA, USA
- Yuan Zhou 0003 — University of South Florida, Department of Mathematics and Statistics, Tampa, FL, USA
- Yuan Zhou 0004 — University of Florida, Department of Computer and Information Science and Engineering, Gainesville, FL, USA
- Yuan Zhou 0005 — Nanyang Technological University, School of Computer Science and Engineering, Singapore (and 1 more)
- Yuan Zhou 0006 — Tianjin University, School of Electrical and Information Engineering, China (and 1 more)
- Yuan Zhou 0007 — Tsinghua University, Yau Mathematical Sciences Center, Beijing, China (and 4 more)
- Yuan Zhou 0008 — Network Emergency Response Technical Team/Coordination Center, China
- Yuan Zhou 0009 — Chinese Academy of Sciences, Institute of Psychology, Beijing, China
- Yuan Zhou 0010 — University of Siegen, Germany
- Yuan Zhou 0012 — University of Illinois Urbana-Champaign, USA
- Yuan Zhou 0013 — University of Oxford, UK
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2020 – today
- 2020
[j7]Yanqing Li, Yuan Zhou, Yun Chiu:
A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits. IEEE Trans. Circuits Syst. 67-II(11): 2327-2331 (2020)
2010 – 2019
- 2019
- [j6]Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu:
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. IEEE J. Solid State Circuits 54(2): 441-451 (2019) - [j5]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. IEEE J. Solid State Circuits 54(8): 2207-2218 (2019) - 2018
- [j4]Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu:
A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS. IEEE J. Solid State Circuits 53(3): 839-849 (2018) - 2017
- [j3]Benwei Xu, Yuan Zhou, Yun Chiu:
A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS. IEEE J. Solid State Circuits 52(4): 1091-1100 (2017) - [c6]Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu:
28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS. ISSCC 2017: 476-477 - 2016
- [c5]Benwei Xu, Yuan Zhou, Yun Chiu:
A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j2]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. IEEE J. Solid State Circuits 50(4): 920-931 (2015) - [j1]Sudipta Sarkar, Yuan Zhou, Brian Elies, Yun Chiu:
PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 654-661 (2015) - 2014
- [c4]Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu:
A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system. CICC 2014: 1-4 - [c3]Sudipta Sarkar, Yuan Zhou, Yun Chiu:
PN-assisted deterministic digital calibration of split two-step ADC to over 14-bit accuracy. MWSCAS 2014: 1049-1052 - [c2]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration. VLSIC 2014: 1-2 - 2013
- [c1]Yuan Zhou, Yun Chiu:
Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC. MWSCAS 2013: 677-680
Coauthor Index
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