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S. Potla

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1990 – 1999

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1996
[c2]
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R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla:
Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. VLSI Design 1996: 156-161
1995
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Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh:
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. VLSI Design 1995: 192-

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