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ORCIDClaude Chappert
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2010 – 2019
- 2015
[j11]Wang Kang, Liuyang Zhang, Weisheng Zhao, Jacques-Olivier Klein
, Youguang Zhang, Dafine Ravelosona, Claude Chappert:
Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 28-39 (2015)- [j10]Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao:
Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. ACM J. Emerg. Technol. Comput. Syst. 12(2): 16:1-16:42 (2015) - 2014
- [j9]Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert:
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. J. Parallel Distributed Comput. 74(6): 2484-2496 (2014) - [j8]Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert:
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 443-454 (2014) - [j7]Djaafar Chabi, Weisheng Zhao, Erya Deng, Yue Zhang, Nesrine Ben Romdhane, Jacques-Olivier Klein, Claude Chappert:
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1755-1765 (2014) - [c21]Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert:
An overview of spin-based integrated circuits. ASP-DAC 2014: 676-683 - [c20]Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert:
Spintronics for low-power computing. DATE 2014: 1-6 - [c19]Zhaohao Wang, Weisheng Zhao, Wang Kang, Youguang Zhang, Jacques-Olivier Klein, Claude Chappert:
Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture. IJCNN 2014: 29-34 - 2013
- [j6]Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona:
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. Microelectron. Reliab. 53(9-11): 1224-1229 (2013) - [j5]Hong-Phuc Trinh, Weisheng Zhao, Jacques-Olivier Klein, Yue Zhang, Dafine Ravelosona, Claude Chappert:
Magnetic Adder Based on Racetrack Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1469-1477 (2013) - [c18]Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao:
Analytical study of complementary memristive synchronous logic gates. NANOARCH 2013: 70-75 - [c17]Djaafar Chabi, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Claude Chappert:
Low power magnetic flip-flop based on checkpointing and self-enable mechanism. NEWCAS 2013: 1-4 - [c16]Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller:
Synchronous full-adder based on complementary resistive switching memory cells. NEWCAS 2013: 1-4 - [c15]Weisheng Zhao, Guillaume Prenat, Jacques-Olivier Klein, Bernard Dieny, Claude Chappert, Dafine Ravelosona:
Emerging hybrid logic circuits based on non-volatile magnetic memories. NEWCAS 2013: 1-4 - [c14]Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang, Nesrine Ben Romdhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert:
Spin-electronics based logic fabrics. VLSI-SoC 2013: 174-179 - 2012
- [j4]Weisheng Zhao, Yue Zhang, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer:
Failure and reliability analysis of STT-MRAM. Microelectron. Reliab. 52(9-10): 1848-1852 (2012) - [c13]Weisheng Zhao, Damien Querlioz, Jacques-Olivier Klein, Djaafar Chabi, Claude Chappert:
Nanodevice-based novel computing paradigms and the neuromorphic approach. ISCAS 2012: 2509-2512 - [c12]Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert:
MRAM crossbar based configurable logic block. ISCAS 2012: 2945-2948 - [c11]Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller:
Crossbar architecture based on 2R complementary resistive switching memory cell. NANOARCH 2012: 85-92 - [i1]Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer:
Cross-point architecture for spin transfer torque magnetic random access memory. CoRR abs/1202.1782 (2012) - 2011
- [j3]Weisheng Zhao, Thibaut Devolder, Yahya Lakys, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer:
Design considerations and strategies for high-reliable STT-MRAM. Microelectron. Reliab. 51(9-11): 1454-1458 (2011) - [c10]Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert:
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power. ARC 2011: 275-280 - [c9]Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitório Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert:
Design of MRAM based logic circuits and its applications. ACM Great Lakes Symposium on VLSI 2011: 431-436 - [c8]Weisheng Zhao, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert:
High Performance SoC Design Using Magnetic Logic and Memory. VLSI-SoC (Selected Papers) 2011: 10-33 - [c7]Weisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli:
Embedded MRAM for high-speed computing. VLSI-SoC 2011: 37-42 - 2010
- [c6]Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer:
High Density Asynchronous LUT Based on Non-volatile MRAM Technology. FPL 2010: 374-379 - [c5]Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer:
Design of embedded MRAM macros for memory-in-logic applications. ACM Great Lakes Symposium on VLSI 2010: 155-158
2000 – 2009
- 2009
- [j2]Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer:
Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit. ACM Trans. Embed. Comput. Syst. 9(2): 14:1-14:16 (2009) - [j1]Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat:
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. ACM Trans. Reconfigurable Technol. Syst. 2(2): 8:1-8:19 (2009) - 2008
- [c4]Franck Badets, Lieven Lagae, Sven Cornelissen, Thibaut Devolder, Claude Chappert:
Injection locked CMOS buffer dedicated to nanomagnetic based voltage controlled oscillator. ICECS 2008: 190-193 - [c3]Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer:
Spintronic Device Based Non-volatile Low Standby Power SRAM. ISVLSI 2008: 40-45 - 2007
- [c2]Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert:
TAS-MRAM based Non-volatile FPGA logic circuit. FPT 2007: 153-160 - [c1]Jacques-Olivier Klein, Eric Belhaire, Claude Chappert, Florent Ouchet, Russell Cowburn, Dan Read, Dorothee Petit:
Synthesis of Finite State Machines with Magnetic Domain Wall Logic. ISCAS 2007: 133-136
Coauthor Index
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