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ORCIDJuan A. Michell
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Journal Articles
- 2013
[j10]Miguel A. Manzano, Juan A. Michell, Gustavo A. Ruiz
:
A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC. J. Signal Process. Syst. 70(1): 59-73 (2013)- [j9]Gustavo A. Ruiz, Juan A. Michell:
Optimized Hardware Implementation for Forward Quantization of H.264/AVC. J. Signal Process. Syst. 72(1): 35-41 (2013) - 2011
- [j8]Juan A. Michell, José M. Solana, Gustavo A. Ruiz:
A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC. Signal Process. Image Commun. 26(2): 93-104 (2011) - [j7]Gustavo A. Ruiz, Juan A. Michell:
An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC. Signal Process. Image Commun. 26(6): 289-303 (2011) - [j6]Gustavo A. Ruiz, Juan A. Michell:
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV. J. Signal Process. Syst. 62(3): 443-457 (2011) - 2006
- [j5]Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón:
High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip. J. VLSI Signal Process. 45(3): 161-175 (2006) - 2005
- [j4]Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón:
Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding. IEEE Trans. Signal Process. 53(2-1): 714-723 (2005) - 1999
- [j3]Jesús García, Juan A. Michell, Angel M. Burón:
VLSI configurable delay commutator for a pipeline split radix FFT architecture. IEEE Trans. Signal Process. 47(11): 3098-3107 (1999) - 1998
- [j2]Gustavo A. Ruiz, Juan A. Michell:
Memory efficient programmable processor chip for inverse Haar transform. IEEE Trans. Signal Process. 46(1): 263-268 (1998) - 1995
- [j1]R. Pereira, Juan A. Michell, José M. Solana:
Fully pipelined TSPC barrel shifter for high-speed applications. IEEE J. Solid State Circuits 30(6): 686-690 (1995)
Conference and Workshop Papers
- 2005
- [c2]Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón:
High throughput 2D DCT/IDCT processor for video coding. ICIP (3) 2005: 1036-1039 - 2003
- [c1]Juan A. Michell, Gustavo A. Ruiz, Angel M. Burón:
Parallel-pipelined architecture for 2-D ICT VLSI implementation. ICIP (3) 2003: 89-92
Coauthor Index
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