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ORCIDToshishige Shimamura
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2010 – 2019
- 2014
[j7]Hiroki Morimura, Shoichi Oshima, Kenichi Matsunaga, Toshishige Shimamura, Mitsuru Harada:
Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting. IEICE Electron. Express 11(20): 20142009 (2014)- 2012
- [c4]Shoichi Oshima, Kenichi Matsunaga, Toshishige Shimamura, Hiroki Morimura, Mitsuru Harada:
1-cm3 event-driven wireless sensor nodes. ICCS 2012: 6-10 - 2011
- [j6]Mamoru Ugajin, Toshishige Shimamura, Shin'ichiro Mutoh, Mitsuru Harada:
Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes. IEICE Trans. Electron. 94-C(7): 1206-1211 (2011) - 2010
- [j5]Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida:
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. IEEE J. Solid State Circuits 45(5): 1080-1087 (2010) - [c3]Toshishige Shimamura, Mamoru Ugajin, Kenji Suzuki, Kazuyoshi Ono, Norio Sato, Kei Kuwabara, Hiroki Morimura, Shin'ichiro Mutoh:
Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications. ISSCC 2010: 504-505
2000 – 2009
- 2008
- [c2]Toshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata
, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi:
A Fingerprint Sensor with Impedance Sensing for Fraud Detection. ISSCC 2008: 170-171 - 2007
- [j4]Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi:
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. IEICE Trans. Electron. 90-C(10): 1892-1899 (2007) - 2006
- [j3]Satoshi Shigematsu, Koji Fujii, Hiroki Morimura, Takahiro Hatano, Mamoru Nakanishi, Namiko Ikeda, Toshishige Shimamura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi:
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Trans. Electron. 89-C(4): 540-550 (2006) - 2005
- [j2]Takakuni Douseki, Toshishige Shimamura, Nobutaro Shibata:
A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation. IEICE Trans. Electron. 88-C(4): 582-588 (2005) - 2002
- [j1]Hiroki Morimura, Satoshi Shigematsu, Toshishige Shimamura, Katsuyuki Machida, Hakaru Kyuragi:
A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs. IEEE J. Solid State Circuits 37(10): 1300-1306 (2002) - [c1]Koji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi:
A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification. CICC 2002: 261-264
Coauthor Index
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