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ORCIDFrank Lee 0004
Person information
- affiliation: Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan
Other persons with the same name
- Frank Lee — disambiguation page
- Frank J. Lee 0001
![[0000-0003-0475-2552]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-0475-2552")
(aka: Frank Lee 0001) — Drexel University, Philadelphia, PA, USA (and 2 more) - Frank J. Lee 0002 (aka: Frank Lee 0002) — Hewlett-Packard Laboratories, Palo Alto, CA, USA
- Frank Lee 0003 — Synopsys Inc., Mountain View, CA, USA (and 1 more)
- Frank Lee 0005 — Georgia State University, College of Business, Atlanta, GA, USA (and 2 more)
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Journal Articles
- 2020
[j1]Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. IEEE J. Solid State Circuits 55(4): 956-966 (2020)
Conference and Workshop Papers
- 2024
- [c13]Sandeep Kumar Goel, Ankita Patidar, Frank Lee:
Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact. ETS 2024: 1-4 - [c12]Sandeep Kumar Goel, Moiz Khan, Ankita Patidar, Frank Lee, Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, Manish Arora:
Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests. ITC 2024: 51-55 - [c11]Sandeep Kumar Goel, Ankita Patidar, Moiz Khan, Frank Lee, Anshuman Chandra, Martin Keim, Naim Lemar, Jonathan Gaudet, Quoc Phan, Vidya Neerkundar:
Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard. ITC 2024: 451-459 - [c10]Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Tze-Chiang Huang, Wen-Hung Huang, Kate Huang, Yu-Chi Chen, Alex Liu, Yu-Jie Huang, Jimmy Wang, Shu-Chun Yang, Nai-Chen Cheng, Chao-Chieh Li, Hsin-Hung Kuo, Wei-Chih Chen, Chin-Hua Wen, Kevin Lin, Po-Yi Huang, Kenny Cheng-Hsiang Hsieh, Frank Lee:
A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. VLSI Technology and Circuits 2024: 1-2 - [c9]Tsung-Che Lu, Chin-Ming Fu, Wei-Hsiang Wang, Fred Kuo, Chih-Hsien Chang, Kenny Hsieh, King-Ho Tam, Tze-Chiang Huang, Tom Chen, Mei Wong, Wei-pin Changchien, Frank Lee:
An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology. VLSI Technology and Circuits 2024: 1-2 - 2021
- [c8]Shenggao Li, Chien-Chun Tsai, Eric Soenen, Frank J. C. Lee, Cheng-Hsiang Hsieh:
Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling. A-SSCC 2021: 1-3 - [c7]Frank J. C. Lee:
Physical Design for 3D Chiplets and System Integration. ISPD 2021: 1 - 2019
- [c6]Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. VLSI Circuits 2019: 28- - 2015
- [c5]Zipeng Li, Sandeep Kumar Goel, Frank Lee, Krishnendu Chakrabarty:
Efficient observation-point insertion for diagnosability enhancement in digital circuits. ITC 2015: 1-10 - 2014
- [c4]Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee:
Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs. VLSI-DAT 2014: 1-4 - 2013
- [c3]Frank Lee, Bill Shen, Willy Chen, Suk Lee:
3DIC from concept to reality. ASP-DAC 2013: 394-398 - [c2]Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim:
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC 2013: 1-10 - 2012
- [c1]Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen:
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10
Coauthor Index
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