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Juan Carlos Diaz

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Journal Articles

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1996
[j1]
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  - journals/tvlsi/PlazaMDC96
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  - https://dblp.org/rec/journals/tvlsi/PlazaMDC96
Pierre Plaza, Luis A. Merayo, Juan Carlos Diaz, José Luis Conesa:
A 2.5 Gb/s ATM switch chip set. IEEE Trans. Very Large Scale Integr. Syst. 4(3): 405-416 (1996)

Conference and Workshop Papers

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1999
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Jacobo Riesco, Juan Carlos Diaz, Pierre Plaza:
The μPP ASIC: design, methodologies and tools for a pay phone system-on-a-chip based on an ARM core and design reuse. CICC 1999: 635-638
1998
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Juan Carlos Diaz, Pierre Plaza, Jesus Crespo:
ATM Traffic Shaper: ATS. DATE 1998: 96-101
[c3]
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Jesus Crespo, Juan Carlos Diaz, Pimitivo Matas:
FPGA Implementation of an ATM Traffic Shaper: ATS (Abstract). FPGA 1998: 262
1997
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Jacobo Riesco, Juan Carlos Diaz, Luis A. Merayo, José Luis Conesa, Carlos Santos, Eduardo Juárez Martínez:
On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC. ED&TC 1997: 218-222
1995
[c1]
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Pierre Plaza, Juan Carlos Diaz, Fermín Calvo, Luis A. Merayo, Maurizio Zamboni, Pietro Scarfone, Marco Barbini:
Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC. ED&TC 1995: 162-166

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