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2020 – today
- 2022
[c4]Wilfred Gomes, Altug Koker, Patrick N. Stover, Doug B. Ingerly, Scott Siers, Srikrishnan Venkataraman, Chris Pelto, Tejas Shah, Amreesh Rao, Frank O'Mahony, Eric Karl, Lance Cheney, Iqbal Rajwani, Hemant Jain, Ryan Cortez, Arun Chandrasekhar, Basavaraj Kanthi, Raja Koduri:
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing. ISSCC 2022: 42-44- 2020
- [c3]Chetan Prasad, Sunny Chugh, Hannes Greve, I-chen Ho, Enamul Kabir, Cheyun Lin, Mahjabin Maksud, Steven R. Novak, Benjamin Orr, Keun Woo Park, Anthony Schmitz, Zhizheng Zhang, Peng Bai, Doug B. Ingerly, Emre Armagan, Hsinwei Wu, Patrick N. Stover, Lance Hibbeler, Michael O'Day, Daniel Pantuso:
Silicon Reliability Characterization of Intel's Foveros 3D Integration Technology for Logic-on-Logic Die Stacking. IRPS 2020: 1-5 - [c2]Wilfred Gomes, Sanjeev Khushu, Doug B. Ingerly, Patrick N. Stover, Nasirul I. Chowdhury, Frank O'Mahony, Ajay Balankutty, Noam Dolev, Martin G. Dixon, Lei Jiang, Surya Prekke, Biswajit Patra, Pavel V. Rott, Rajesh Kumar:
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package. ISSCC 2020: 144-146
2010 – 2019
- 2015
- [c1]Chia-Hong Jan, F. Al-amoody, H.-Y. Chang, T. Chang, Y.-W. Chen, N. Dias, Walid M. Hafez, Doug B. Ingerly, M. Jang, Eric Karl, S. K.-Y. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C.-G. Lee, J. Lee, T. Leo, P.-C. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, Chetan Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, Aravinth Subramaniam, C. Tsai, Peter Vandervoorn, L. Yang, A. Zainuddin, Peng Bai:
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. VLSIC 2015: 12-
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