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2020 – today
- 2023
[c3]Saloni Bansal, V. K. Tomar:
10T SRAM cell Analysis for improved Read and Write Noise Margin. ICCCNT 2023: 1-7- 2022
- [j9]Ashish Sachdeva
, V. K. Tomar:
Characterization of Stable 12T SRAM with Improved Critical Charge. J. Circuits Syst. Comput. 31(2): 2250023:1-2250023:34 (2022) - [j8]Harekrishna Kumar, V. K. Tomar:
Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices. J. Circuits Syst. Comput. 31(2): 2250027:1-2250027:28 (2022) - [j7]V. K. Tomar, Ashish Sachdeva:
Design of a soft error hardened SRAM cell with improved access time for embedded systems. Microprocess. Microsystems 90: 104445 (2022) - 2021
- [j6]Ashish Sachdeva, V. K. Tomar:
Design of 10T SRAM cell with improved read performance and expanded write margin. IET Circuits Devices Syst. 15(1): 42-64 (2021) - [j5]Ashish Sachdeva, V. K. Tomar:
Design of Low Power Half Select Free 10T Static Random-Access Memory Cell. J. Circuits Syst. Comput. 30(4): 2150073:1-2150073:32 (2021) - [j4]Harekrishna Kumar, V. K. Tomar:
Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices. J. Circuits Syst. Comput. 30(6): 2150106:1-2150106:30 (2021) - [j3]Harekrishna Kumar, V. K. Tomar:
A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era. Wirel. Pers. Commun. 117(3): 1959-1984 (2021) - [j2]Ashish Sachdeva, V. K. Tomar:
A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications. Wirel. Pers. Commun. 120(3): 2201-2225 (2021) - 2020
- [j1]Ashish Sachdeva, V. K. Tomar:
Design of a Stable Low Power 11-T Static Random Access Memory Cell. J. Circuits Syst. Comput. 29(13): 2050206:1-2050206:23 (2020) - [c2]Deepak Mittal, V. K. Tomar:
Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node. ICCCNT 2020: 1-4
2010 – 2019
- 2018
- [c1]Reeya Agrawal, V. K. Tomar:
Analysis of Cache(SRAM) Memory for Core i™ 7 Processor. ICCCNT 2018: 1-8
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