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Dhananjaya Wijerathne
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2020 – today
- 2025
[c12]Zhaoying Li, Dan Wu, Dhananjaya Wijerathne, Dan Chen, Huize Li
, Cheng Tan, Tulika Mitra:
Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm. DAC 2025: 1-7
[c11]Rohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Zhaoying Li, Dhananjaya Wijerathne, Li-Shiuan Peh, Tulika Mitra:
Building an Open CGRA Ecosystem for Agile Innovation. ICCAD 2025: 1-9
[i3]Zhenyu Bai
, Dan Wu, Pranav Dangi, Dhananjaya Wijerathne, Venkata Pavan Kumar Miriyala, Tulika Mitra:
Data-aware Dynamic Execution of Irregular Workloads on Heterogeneous Systems. CoRR abs/2502.06304 (2025)
[i2]Rohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Zhaoying Li, Dhananjaya Wijerathne, Li-Shiuan Peh, Tulika Mitra:
Building an Open CGRA Ecosystem for Agile Innovation. CoRR abs/2508.19090 (2025)- 2024
[c10]Pranav Dangi
, Zhenyu Bai
, Rohan Juneja
, Dhananjaya Wijerathne
, Tulika Mitra
:
ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML. PACT 2024: 246-257
[c9]Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja
, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do:
PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications. HCS 2024: 1
[c8]Vishnu P. Nambiar, Y. S. Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Z. Li, Rohan Juneja
, Li-Shiuan Peh, Tulika Mitra, A. T. Do:
A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications. ISOCC 2024: 89-90- 2023
[c7]Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja
, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh:
FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow. ICCAD 2023: 1-9
[i1]Dhananjaya Wijerathne, Zhaoying Li, Tulika Mitra:
Accelerating Edge AI with Morpher: An Integrated Design, Compilation and Simulation Framework for CGRAs. CoRR abs/2309.06127 (2023)- 2022
[j3]Zhaoying Li
, Dhananjaya Wijerathne
, Xianzhang Chen
, Anuj Pathania
, Tulika Mitra
:
ChordMap: Automated Mapping of Streaming Applications Onto CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(2): 306-319 (2022)
[j2]Dhananjaya Wijerathne
, Zhaoying Li
, Anuj Pathania
, Tulika Mitra
, Lothar Thiele
:
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3290-3303 (2022)
[c6]Thilini Kaushalya Bandara
, Dhananjaya Wijerathne
, Tulika Mitra
, Li-Shiuan Peh
:
REVAMP: a systematic framework for heterogeneous CGRA realization. ASPLOS 2022: 918-932
[c5]Dhananjaya Wijerathne, Zhaoying Li, Thilini Kaushalya Bandara, Tulika Mitra:
PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA. DAC 2022: 127-132
[c4]Zhaoying Li
, Dan Wu, Dhananjaya Wijerathne, Tulika Mitra:
LISA: Graph Neural Network based Portable Mapping on Spatial Accelerators. HPCA 2022: 444-459
[c3]Yujie Zhang
, Dhananjaya Wijerathne, Zhaoying Li, Tulika Mitra:
Power-Performance Characterization of TinyML Systems. ICCD 2022: 644-651- 2021
[c2]Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele:
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction. DATE 2021: 1192-1197
2010 – 2019
- 2019
[j1]Dhananjaya Wijerathne, Zhaoying Li, Manupa Karunarathne, Anuj Pathania, Tulika Mitra
:
CASCADE: High Throughput Data Streaming via Decoupled Access-Execute CGRA. ACM Trans. Embed. Comput. Syst. 18(5s): 50:1-50:26 (2019)
[c1]Manupa Karunaratne, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh:
4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs. ICCAD 2019: 1-8
Coauthor Index

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