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Raghavan Kumar
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Journal Articles
- 2024
- [j8]Raghavan Kumar
, Avinash L. Varna
, Carlos Tokunaga, Sachin Taneja
, Vivek De
, Sanu K. Mathew
:
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS. IEEE J. Solid State Circuits 59(1): 79-89 (2024) - 2023
- [j7]Raghavan Kumar
, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal
, Vivek De
, Sanu K. Mathew
:
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. IEEE J. Solid State Circuits 58(4): 1106-1116 (2023) - 2022
- [j6]Debayan Das
, Mayukh Nath
, Baibhab Chatterjee
, Raghavan Kumar
, Xiaosen Liu
, Harish Krishnamurthy
, Manoj R. Sastry, Sanu Mathew
, Santosh Ghosh, Shreyas Sen
:
EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4927-4938 (2022) - 2021
- [j5]Phil C. Knag
, Gregory K. Chen
, Huseyin Ekin Sumbul
, Raghavan Kumar
, Steven K. Hsu, Amit Agarwal
, Monodeep Kar, Seongjong Kim
, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy
:
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 56(4): 1082-1092 (2021) - [j4]Raghavan Kumar
, Xiaosen Liu
, Vikram B. Suresh, Harish K. Krishnamurthy
, Sudhir Satpathy
, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran
, Vivek De
, Sanu K. Mathew
:
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. IEEE J. Solid State Circuits 56(4): 1141-1151 (2021) - 2020
- [j3]Raghavan Kumar
, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy
, Mark A. Anders, Himanshu Kaul, Amit Agarwal
, Steven Hsu, Gregory K. Chen
, Ram K. Krishnamurthy, Vivek De
, Sanu K. Mathew
:
A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE J. Solid State Circuits 55(4): 945-955 (2020) - 2019
- [j2]Gregory K. Chen
, Raghavan Kumar, Huseyin Ekin Sumbul
, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 54(4): 992-1002 (2019) - [j1]Sudhir Satpathy
, Sanu K. Mathew
, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal
, Steven Hsu, Ram K. Krishnamurthy, Vivek De
:
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. IEEE J. Solid State Circuits 54(4): 1074-1085 (2019)
Conference and Workshop Papers
- 2024
- [c45]Sirish Oruganti, Meizhi Wang, Vishnuvardhan V. Iyer, Yipeng Wang, Mengtian Yang, Raghavan Kumar, Sanu K. Mathew, Jaydeep P. Kulkarni:
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits. ISSCC 2024: 308-310 - 2023
- [c44]Anuj Dubey, Rosario Cammarota, Avinash Varna, Raghavan Kumar, Aydin Aysu:
Hardware-Software Co-design for Side-Channel Protected Neural Network Inference. HOST 2023: 155-166 - [c43]Raghavan Kumar, Avinash Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu Mathew:
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. ISSCC 2023: 244-245 - [c42]Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew:
218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c41]Prathyush Poduval, Yang Ni, Yeseong Kim, Kai Ni, Raghavan Kumar, Rosario Cammarota, Mohsen Imani:
Adaptive neural recovery for highly robust brain-like representation. DAC 2022: 367-372 - [c40]Meizhi Wang
, Sirish Oruganti, Shanshan Xie, Raghavan Kumar, Sanu Mathew, Jaydeep P. Kulkarni:
Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks. ESSCIRC 2022: 529-532 - [c39]Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu, Amit Agarwal, Vivek K. De, Sanu K. Mathew:
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS. ISSCC 2022: 1-3 - [c38]Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew:
A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. VLSI Technology and Circuits 2022: 138-139 - 2021
- [c37]Meizhi Wang
, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni:
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks. CICC 2021: 1-2 - 2020
- [c36]Vikram B. Suresh, Raghavan Kumar, Sanu Mathew:
INVITED: A 0.26% BER, Machine-Learning Resistant 1028 Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. DAC 2020: 1-3 - [c35]Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De:
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC 2020: 392-394 - [c34]Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De:
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC 2020: 396-398 - [c33]Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De:
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits 2020: 1-2 - [c32]Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De:
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits 2020: 1-2 - [c31]Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy:
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2 - [c30]Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish Krishnamurthy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu Mathew:
A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. VLSI Circuits 2020: 1-2 - [c29]Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew:
A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. VLSI Circuits 2020: 1-2 - [c28]Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah
, Jim Tschanz, Vivek De:
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits 2020: 1-2 - [c27]Vikram B. Suresh, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew:
A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. VLSI Circuits 2020: 1-2 - 2019
- [c26]Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC 2019: 137-140 - [c25]Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Kirk Yap, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew:
A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. CICC 2019: 1-4 - [c24]Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew:
A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. CICC 2019: 1-4 - [c23]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca
, Martin Langhammer, Debbie Marr, Aravind Dasu:
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM 2019: 199-207 - [c22]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca
, Martin Langhammer, Aravind Dasu:
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA 2019: 119 - [c21]Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. VLSI Circuits 2019: 32- - [c20]Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits 2019: 50- - [c19]Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. VLSI Circuits 2019: 234- - [c18]Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. VLSI Circuits 2019: 238- - 2018
- [c17]Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS. VLSI Circuits 2018: 255-256 - 2015
- [c16]Raghavan Kumar, Wayne P. Burleson:
Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data. RFIDSec 2015: 53-67 - 2014
- [c15]Victor Tomashevich, Yaara Neumeier, Raghavan Kumar, Osnat Keren, Ilia Polian:
Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. DFT 2014: 40-45 - [c14]Raghavan Kumar, Philipp Jovanovic, Wayne P. Burleson, Ilia Polian:
Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. FDTC 2014: 18-28 - [c13]Raghavan Kumar, Wayne P. Burleson:
On design of a highly secure PUF based on non-linear current mirrors. HOST 2014: 38-43 - [c12]Raghavan Kumar, Wayne P. Burleson:
Hybrid modeling attacks on current-based PUFs. ICCD 2014: 493-496 - [c11]Raghavan Kumar, Philipp Jovanovic, Ilia Polian:
Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. IOLTS 2014: 43-48 - [c10]Xiaolin Xu, Vikram B. Suresh, Raghavan Kumar, Wayne P. Burleson:
Post-Silicon Validation and Calibration of Hardware Security Primitives. ISVLSI 2014: 29-34 - [c9]Raghavan Kumar, Siva Nishok Dhanuskodi, Sandip Kundu:
On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions. VLSID 2014: 381-386 - 2013
- [c8]Raghavan Kumar, Wayne P. Burleson:
Litho-aware and low power design of a secure current-based physically unclonable function. ISLPED 2013: 402-407 - [c7]Arunachalam Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, Sandip Kundu:
A system-level solution for managing spatial temperature gradients in thinned 3D ICs. ISQED 2013: 88-95 - [c6]Sudarshan Srinivasan, Raghavan Kumar, Sandip Kundu:
Program phase duration prediction and its application to fine-grain power management. ISVLSI 2013: 127-132 - 2012
- [c5]Arunkumar Vijayakumar, Raghavan Kumar, Sandip Kundu:
On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors. ISVLSI 2012: 120-125 - [c4]Raghavan Kumar, Vinay C. Patil, Sandip Kundu:
On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators. ISVLSI 2012: 165-170 - [c3]Raghavan Kumar, Wayne P. Burleson:
PHAP: Password based Hardware Authentication using PUFs. MICRO Workshops 2012: 24-31 - 2011
- [c2]Raghavan Kumar, Harikrishnan Kumarapillai Chandrikakutty, Sandip Kundu:
On improving reliability of delay based Physically Unclonable Functions under temperature variations. HOST 2011: 142-147 - [c1]Raghavan Kumar, Vinay C. Patil, Sandip Kundu:
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain. ISVLSI 2011: 224-229
Informal and Other Publications
- 2023
- [i4]Anuj Dubey, Rosario Cammarota, Avinash Varna, Raghavan Kumar, Aydin Aysu:
Hardware-Software Co-design for Side-Channel Protected Neural Network Inference. IACR Cryptol. ePrint Arch. 2023: 163 (2023) - 2014
- [i3]Georg T. Becker, Raghavan Kumar:
Active and Passive Side-Channel Attacks on Delay Based PUF Designs. IACR Cryptol. ePrint Arch. 2014: 287 (2014) - [i2]Raghavan Kumar, Philipp Jovanovic, Ilia Polian:
Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. IACR Cryptol. ePrint Arch. 2014: 782 (2014) - [i1]Raghavan Kumar, Philipp Jovanovic, Wayne P. Burleson, Ilia Polian:
Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. IACR Cryptol. ePrint Arch. 2014: 783 (2014)
Coauthor Index
aka: Vivek K. De
aka: Steven K. Hsu
aka: Ram K. Krishnamurthy
aka: Sanu K. Mathew
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