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Yutaka Tabuchi
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2020 – today
- 2024
- [j3]Yosuke Ueno
, Yuna Tomida
, Teruo Tanimoto
, Masamitsu Tanaka
, Yutaka Tabuchi
, Koji Inoue
, Hiroshi Nakamura
:
Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. IEEE Comput. Archit. Lett. 23(1): 6-9 (2024) - [i3]Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
SFQ counter-based precomputation for large-scale cryogenic VQE machines. CoRR abs/2403.00363 (2024) - 2023
- [c7]Takefumi Miyoshi, Keisuke Koike, Shinich Morisaka, Hidehisa Shiomi, Ryo Matsuda, Kazuhisa Ogawa, Yutaka Tabuchi, Makoto Negoro:
A Fully Pipelined Architecture of Quantum-Classical Interface for Realizing Fault-Tolerant Quantum Computer. QCE 2023: 322-323 - [i2]Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
Inter-temperature Bandwidth Reduction in Cryogenic QAOA Machines. CoRR abs/2310.01630 (2023) - 2022
- [j2]Shuhei Tamate, Yutaka Tabuchi, Yasunobu Nakamura:
Toward Realization of Scalable Packaging and Wiring for Large-Scale Superconducting Quantum Computers. IEICE Trans. Electron. 105-C(6): 290-295 (2022) - [c6]Takefumi Miyoshi, Keisuke Koike, Shinich Morisaka, Hidehisa Shiomi, Kazuhisa Ogawa, Yutaka Tabuchi, Makoto Negoro:
FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs. FPL 2022: 473 - [c5]Yosuke Ueno
, Masaaki Kondo, Masamitsu Tanaka
, Yasunari Suzuki, Yutaka Tabuchi:
QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery. HPCA 2022: 274-287 - [i1]Yosuke Ueno
, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi:
NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes. CoRR abs/2208.05758 (2022) - 2021
- [c4]Yosuke Ueno
, Masaaki Kondo, Masamitsu Tanaka
, Yasunari Suzuki, Yutaka Tabuchi:
QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code. DAC 2021: 451-456 - [c3]Yutaka Tabuchi, Shuhei Tamate, Shinichi Yorozu:
Superconducting quantum computer: a hint for building architectures. VLSI Circuits 2021: 1-2 - 2020
- [c2]Teruo Tanimoto
, Shuhei Matsuo, Satoshi Kawakami
, Yutaka Tabuchi
, Masao Hirokawa
, Koji Inoue:
How Many Trials Do We Need for Reliable NISQ Computing? ISVLSI 2020: 288-290 - [c1]Teruo Tanimoto
, Shuhei Matsuo, Satoshi Kawakami
, Yutaka Tabuchi
, Masao Hirokawa
, Koji Inoue:
Practical Error Modeling Toward Realistic NISQ Simulation. ISVLSI 2020: 291-293
2010 – 2019
- 2019
- [j1]Yutaka Tabuchi, Shuhei Tamate, Yasunobu Nakamura:
Toward Scalable Superconducting Quantum Computer Implementation. IEICE Trans. Electron. 102-C(3): 212-216 (2019)
Coauthor Index
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