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2020 – today
- 2024
[j2]Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michihiro Shintani:
Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(8): 1139-1150 (2024)- 2021
- [j1]Riaz-ul-haque Mian
, Michihiro Shintani, Michiko Inoue:
Hardware-Software Co-Design for Decimal Multiplication. Comput. 10(2): 17 (2021) - [c3]Michihiro Shintani, Riaz-ul-haque Mian, Michiko Inoue, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki:
Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. ITC 2021: 103-112 - [i2]Michihiro Shintani, Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue:
Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. CoRR abs/2111.01369 (2021) - 2020
- [i1]Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue:
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. CoRR abs/2003.05315 (2020)
2010 – 2019
- 2019
- [c2]Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue:
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. SoCC 2019: 412-417 - 2018
- [c1]Mian Riaz-ul-haque, Michihiro Shintani, Michiko Inoue:
Decimal Multiplication Using Combination of Software and Hardware. APCCAS 2018: 239-242
Coauthor Index
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