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2010 – 2019
- 2019
[c7]Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Yun-Shiang Shu, Pao-Cheng Chiu:
An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS. ISSCC 2019: 334-336- 2016
- [j1]Wei-Hsin Tseng
, Wei-Liang Lee, Chang-Yang Huang, Pao-Cheng Chiu:
A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters. IEEE J. Solid State Circuits 51(10): 2222-2231 (2016) - 2015
- [c6]Wei-Hsin Tseng, Wei-Liang Lee, Chang-Yang Huang, Pao-Cheng Chiu:
A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters. A-SSCC 2015: 1-4 - [c5]Tsung-Kai Kao, Ping Chen, Jui-Yuan Tsai, Pao-Cheng Chiu:
A 16nm FinFet 19/39MHz 78/72dB DR noise-injected aggregated CTSDM ADC for configurable LTE advanced CCA/NCCA Application. VLSIC 2015: 260- - 2014
- [c4]Wei-Hsin Tseng, Pao-Cheng Chiu:
A 960MS/s DAC with 80dB SFDR in 20nm CMOS for multi-mode baseband wireless transmitter. VLSIC 2014: 1-2 - 2013
- [c3]Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu:
A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer. ISSCC 2013: 268-269 - [c2]Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu:
A background calibration technique for fully dynamic flash ADCs. VLSI-DAT 2013: 1-4
2000 – 2009
- 2009
- [c1]Chi-Cheng Ju, Tsu-Ming Liu, Chih-Chieh Yang, Shih-Hung Lin, Kuo-Pin Lan, Chien-Hua Wu, Ting-Hsun Wei, Chi-Chin Lien, Jiun-Yuan Wu, Chih-Hao Hsiao, Te-Wei Chen, Yeh-Lin Chu, Guan-Yi Lin, Yung-Chang Chang, Kung-Sheng Lin, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Chien-Hung Lin, Yung-Teng Lin, Shang-Ming Lee, Ya-Ching Yang, Yu-Lun Cheng, Chen-Chia Lee, Ming-Shiang Lai, Wen-Hua Wu, Ted Hu, Chao-Wei Tseng, Chen-Yu Hsiao, Wei-Liang Lee, Bo-Jiun Chen, Pao-Cheng Chiu, Shang-Ping Chen, Kun-Hsien Li, Kuan-Hua Chao, Chien-Ming Chen, Chuan-Cheng Hsiao, Jeffrey Ju, Wei-Hung Huang, Chi-Hui Wang, Hung-Sung Li, Evan Su, Joe Chen:
A multi-format Blu-ray player SoC in 90nm CMOS. ISSCC 2009: 152-153
Coauthor Index
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