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2010 – 2019
- 2013
[c8]N. Prameela Kumari, Prashant V. Joshi
, K. S. Gurumurthy:
Realization of Basic Gates Using Universal Logic Blocks in Quantum Dot Cellular Automata. ICETET 2013: 50-51- [c7]Prashant V. Joshi, N. Prameela Kumari, K. S. Gurumurthy:
Instruction Level Power Analysis for Low Power VLSI Applications. ICETET 2013: 52-53 - 2012
- [c6]R. Jayagowri, K. S. Gurumurthy:
Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips. VDAT 2012: 52-58 - [i2]Geetishree Mishra, Rajeshwari Hegde, K. S. Gurumurthy:
Deploying Health Monitoring ECU Towards Enhancing the Performance of In-Vehicle Network. CoRR abs/1208.1429 (2012) - 2011
- [c5]K. S. Vasundara Patel, K. S. Gurumurthy:
Design of High Performance Quaternary Adders. ISMVL 2011: 22-26 - 2010
- [j2]Suma S. A., K. S. Gurumurthy:
Sub Band Speech Analysis Using Gammatone Filter Banks and Optimal Pitch Extraction Methods for Each Sub Band Using Average Magnitude Difference Function (AMDF) for LPC Speech Coders in Noisy Environments. J. Next Gener. Inf. Technol. 1(2): 13-24 (2010) - [j1]Suma S. A., K. S. Gurumurthy:
New Improved Echo Canceller Based on Normalized LMS Adaptive Filter for Single Talk and Double Talk Detection, Subband Echo Cancellation, Acoustic Echo Cancellation. J. Next Gener. Inf. Technol. 1(2): 61-74 (2010) - [i1]K. S. Vasundara Patel, K. S. Gurumurthy:
Arithmetic Operations in Multi-Valued Logic. CoRR abs/1003.5442 (2010)
2000 – 2009
- 2009
- [c4]Rajeshwari Hegde, K. S. Gurumurthy:
Load Balancing in Multi ECU Configuration. ARTCom 2009: 103-106 - [c3]Rajeshwari Hegde, K. S. Gurumurthy:
Load Balancing towards ECU Integration. ARTCom 2009: 521-524 - [c2]K. S. Vasundara Patel, K. S. Gurumurthy:
Moving From Binary Towards Multi-valued logic. CDES 2009: 24-30 - 2003
- [c1]R. Manjunath, K. S. Gurumurthy:
Artificial neural networks as building blocks of mixed signal FPGA. FPT 2003: 375-378
Coauthor Index
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