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Journal Articles
- 2022
[j1]Patrick Sittel
, Nicolai Fiege, John Wickerson, Peter Zipf:
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 614-627 (2022)
Conference and Workshop Papers
- 2022
- [c11]Nicolai Fiege, Patrick Sittel, Peter Zipf:
Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling. FCCM 2022: 1-2 - [c10]Nicolai Fiege, Patrick Sittel, Peter Zipf:
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. FPL 2022: 262-269 - [c9]Nicolai Fiege, Patrick Sittel, Peter Zipf:
Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. FPL 2022: 322-326 - 2020
- [c8]Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf:
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. ASP-DAC 2020: 568-573 - 2019
- [c7]Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen:
Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. Euro-Par 2019: 170-183 - [c6]Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf:
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. ReConFig 2019: 1-8 - 2018
- [c5]Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch:
ILP-Based Modulo Scheduling and Binding for Register Minimization. FPL 2018: 265-271 - [c4]Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf:
Constant Matrix Multiplication with Ternary Adders. ICECS 2018: 85-88 - [c3]Patrick Sittel, Thomas Schönwälder, Martin Kumm, Peter Zipf:
ScaLP: A Light-Weighted (MI)LP-Library. MBMV 2018 - 2017
- [c2]Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis:
Model-based hardware design based on compatible sets of isomorphic subgraphs. FPT 2017: 199-202 - [c1]Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf:
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. MBMV 2017: 103-114
Coauthor Index
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