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ORCIDYangyi Zhang 0002
Person information
- affiliation: Southern University of Science and Technology, School of Microelectronics, Shenzhen, China
Other persons with the same name
- Yangyi Zhang — disambiguation page
- Yangyi Zhang 0001
![[0009-0001-0944-1596]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0009-0001-0944-1596")
— Army Engineering University of PLA, College of Communications Engineering, Nanjing, China
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2020 – today
- 2025
[j8]Liping Zhong, Hongzhi Wu, Yangyi Zhang, Xuxu Cheng, Weitao Wu, Catherine Wang, Xiongshi Luo, Taiyang Fan, Dongfan Xu, Zhenghao Li, Quan Pan:
A 2 × 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS. IEEE J. Solid State Circuits 60(7): 2632-2644 (2025)- [j7]Hongzhi Wu, Liping Zhong, Weitao Wu, Catherine Wang, Xuxu Cheng, Xiongshi Luo, Yangyi Zhang, Dongfan Xu, Quan Pan:
A 2 × 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS. IEEE J. Solid State Circuits 60(8): 2959-2970 (2025) - [j6]Xiongshi Luo, Xuewei You, Jiahan Fu, Zhenghao Li, Liping Zhong, Mengjie Song, Taiyang Fan, Wenbo Xiao, Hongzhi Wu, Yangyi Zhang, Chenchang Zhan, Quan Pan:
A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. IEEE Trans. Circuits Syst. I Regul. Pap. 72(12): 7681-7692 (2025) - [j5]Yangyi Zhang, Xianglong Wang, Lei Chen, Fengwei An:
ReHIT: Reconfigurable High-Radix Iterative-Taylor Architecture for Ultraprecise Logarithm/Exponential Functions in FPGA-Based Softmax Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 33(10): 2690-2701 (2025) - [c13]Hongzhi Wu, Xuxu Cheng, Liping Zhong, Yangyi Zhang, Weitao Wu, Xiongshi Luo, Quan Pan:
A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS. CICC 2025: 1-3 - [c12]Yangyi Zhang, Zhenyu Yao, Wentao Zhou, Xiongshi Luo, Zhenghao Li, Dongshen Zhan, Quan Pan:
36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD-TIA Reach in 28nm CMOS. ISSCC 2025: 1-3 - 2024
- [j4]Liping Zhong, Hongzhi Wu, Weitao Wu, Catherine Wang, Wenbo Xiao, Xiongshi Luo, Yangyi Zhang, Dongfan Xu, Wei Wang, Taiyang Fan, Zhenghao Li, Xuxu Cheng, Quan Pan:
A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS. IEEE J. Solid State Circuits 59(9): 3008-3020 (2024) - [c11]Wei Zhang, Yiwei Luo, Yangyi Zhang, Jiaqi Ouyang, Guodong Wang, Xianglong Wang, Gang Shi, Lei Chen, Fengwei An:
A 43.3 bit/cycle Inflate Accelerator Featuring Static-Dynamic Huffman Decoder with Multiple Checkpoints and Optimized End-Of-Block Control for Hyperscale data. A-SSCC 2024: 1-3 - [c10]Hongzhi Wu, Weitao Wu, Liping Zhong, Xuxu Cheng, Yangyi Zhang, Xiongshi Luo, Dongfan Xu, Xindan Yu, Quan Pan:
A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS. CICC 2024: 1-2 - [c9]Ruoheng Yao, Shengming Zhou, Zhiyue Gao, Yangyi Zhang, Yiwei Luo, Lei Chen, Fengwei An:
Live Demonstration: A Video Denoising Co-processor with Non-local Means Algorithm for FHD 30fps Image Sensor. ISCAS 2024: 1 - [c8]Liping Zhong, Hongzhi Wu, Yangyi Zhang, Xuxu Cheng, Weitao Wu, Catherine Wang, Xiongshi Luo, Taiyang Fan, Dongfan Xu, Quan Pan:
7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS. ISSCC 2024: 134-136 - [c7]Liping Zhong, Yangyi Zhang, Xiongshi Luo, Hongzhi Wu, Xuxu Cheng, Weitao Wu, Zhenghao Li, Quan Pan:
A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j3]Yangyi Zhang, Xianglong Wang, Gang Shi, Zizhao Peng, Lei Chen, Fengwei An:
Anti-Aliasing and Anti-Color-Artifact Demosaicing for High-Resolution CMOS Image Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4928-4937 (2023) - [j2]Dongfan Xu, Yangyi Zhang, Xiongshi Luo, Zhenghao Li, Quan Pan:
A 0.96-0.9-V Fully Integrated FVF LDO With Two-Stage Cross-Coupled Error Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3757-3761 (2023) - [c6]Dongshen Zhan, Liping Zhong, Wentao Zhou, Zhenyu Yao, Xiongshi Luo, Yangyi Zhang, Hemiao Wang, De Zhou, Quan Pan:
A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS. ICTA 2023: 192-193 - [c5]Dongfan Xu, Yangyi Zhang, Zhenghao Li, Xiongshi Luo, Pingyi Cai, Hongzhi Wu, Liping Zhong, Weitao Wu, Liru Zhu, Quan Pan:
A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS. ISCAS 2023: 1-4 - 2022
- [j1]Pingcheng Dong, Zhuoyu Chen, Zhuoao Li, Ruoheng Yao, Wenyue Zhang, Yangyi Zhang, Lei Chen, Chao Wang, Fengwei An:
Configurable Image Rectification and Disparity Refinement for Stereo Vision. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 3973-3977 (2022) - 2021
- [c4]Pingcheng Dong, Zhuoao Li, Zhuoyu Chen, Ruoheng Yao, Huanshihong Deng, Wenyue Zhang, Yangyi Zhang, Lei Chen, Chao Wang, Fengwei An:
A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching. A-SSCC 2021: 1-3 - [c3]Ruoheng Yao, Huanshihong Deng, Wenyue Zhang, Yangyi Zhang, Lei Chen, Fengwei An:
A Pseudo 943 million Frames Per Rate High-Speed Camera with Asynchronous Double-Frame Exposure for Motion Estimation. ICTA 2021: 103-104 - [c2]Yangyi Zhang, Zizhao Peng, Ruoheng Yao, Huanshihong Deng, Wenyue Zhang, Lei Chen, Fengwei An:
Efficient VLSI Architecture for Edge Sensing Anti-Aliasing Demosaicing. ICTA 2021: 105-106 - 2020
- [c1]Huanshihong Deng, Pingcheng Dong, Zhuoao Li, Haoran Lyu, Yangyi Zhang, Yiwei Luo, Fengwei An:
Robot navigation based on pseudo-binocular stereo vision and linear fitting. ICTA 2020: 174-175
Coauthor Index
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