"A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order ..."

Liping Zhong et al. (2024)

> Home

Details and statistics

DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631489

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/ZhongZLWCWL024
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/ZhongZLWCWL024
Liping Zhong, Yangyi Zhang, Xiongshi Luo, Hongzhi Wu, Xuxu Cheng, Weitao Wu, Zhenghao Li, Quan Pan:
A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. VLSI Technology and Circuits 2024: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.