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2020 – today
- 2023
[c18]Priyanka Darke, Bharti Chimdyalwar:
OLA: Property Directed Outer Loop Abstraction for Efficient Verification of Reactive Systems. ICSME 2023: 436-440- [c17]Priyanka Darke
, Bharti Chimdyalwar, Sakshi Agrawal, Shrawan Kumar, R. Venkatesh, Supratik Chakraborty:
VeriAbsL: Scalable Verification by Abstraction and Strategy Prediction (Competition Contribution). TACAS (2) 2023: 588-593 - 2022
- [c16]Vaidehi Ghime, Ankita Khadsare, Anushri Jana, Bharti Chimdyalwar:
IR Mapping: Intermediate Representation (IR) based Mapping to facilitate Incremental Static Analysis. ISEC 2022: 23:1-23:5 - [c15]Anushri Jana, Bharti Chimdyalwar, Shrawan Kumar, R. Venkatesh:
Fast Analysis of Evolving Software Systems. ISSRE Workshops 2022: 49-54 - [c14]Bharti Chimdyalwar, Anushri Jana, Shrawan Kumar, Ankita Khadsare, Vaidehi Ghime:
Identifying Relevant Changes for Incremental Verification of Evolving Software Systems. SANER 2022: 657-661 - 2021
- [c13]Anushri Jana, Ankita Khadsare, Bharti Chimdyalwar, Shrawan Kumar, Vaidehi Ghime, R. Venkatesh:
Fast Change-Based Alarm Reporting for Evolving Software Systems. ISSRE 2021: 546-556 - [c12]Bharti Chimdyalwar, Shrawan Kumar:
Selective path-sensitive interval analysis (WIP paper). LCTES 2021: 146-150 - 2020
- [c11]Mohammad Afzal, Supratik Chakraborty, Avriti Chauhan, Bharti Chimdyalwar, Priyanka Darke, Ashutosh Gupta, Shrawan Kumar, Charles Babu M, Divyesh Unadkat, R. Venkatesh:
VeriAbs : Verification by Abstraction and Test Generation (Competition Contribution). TACAS (2) 2020: 383-387
2010 – 2019
- 2019
- [c10]Mohammad Afzal, Asia A, Avriti Chauhan, Bharti Chimdyalwar, Priyanka Darke, Advaita Datar, Shrawan Kumar, R. Venkatesh:
VeriAbs : Verification by Abstraction and Test Generation. ASE 2019: 1138-1141 - 2018
- [c9]Bharti Chimdyalwar, Priyanka Darke:
Statically relating program properties for efficient verification (short WIP paper). LCTES 2018: 99-103 - [c8]Priyanka Darke, Sumanth Prabhu, Bharti Chimdyalwar, Avriti Chauhan, Shrawan Kumar, Animesh Basak Chowdhury, R. Venkatesh, Advaita Datar, Raveendra Kumar Medicherla:
VeriAbs: Verification by Abstraction and Test Generation - (Competition Contribution). TACAS (2) 2018: 457-462 - 2017
- [c7]Priyanka Darke, Bharti Chimdyalwar, Avriti Chauhan, R. Venkatesh:
Efficient Safety Proofs for Industry-Scale Code Using Abstractions and Bounded Model Checking. ICST 2017: 468-475 - [c6]Bharti Chimdyalwar, Priyanka Darke, Avriti Chauhan, Punit Shah, Shrawan Kumar, R. Venkatesh:
VeriAbs: Verification by Abstraction (Competition Contribution). TACAS (2) 2017: 404-408 - 2015
- [c5]Priyanka Darke, Bharti Chimdyalwar, R. Venkatesh, Ulka Shrotri, Ravindra Metta:
Over-approximating loops to prove properties using bounded model checking. DATE 2015: 1407-1412 - [c4]Bharti Chimdyalwar, Priyanka Darke, Anooj Chavda, Sagar Vaghani, Avriti Chauhan:
Eliminating Static Analysis False Positives Using Loop Abstraction and Bounded Model Checking. FM 2015: 573-576 - 2013
- [c3]Shrawan Kumar, Bharti Chimdyalwar, Ulka Shrotri:
Precise range analysis on large industry code. ESEC/SIGSOFT FSE 2013: 675-678 - 2012
- [c2]Bharti Chimdyalwar:
Survey of array out of bound access checkers for C code. ISEC 2012: 45-48 - 2011
- [c1]Bharti Chimdyalwar, Shrawan Kumar:
Effective false positive filtering for evolving software. ISEC 2011: 103-106
Coauthor Index
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