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Journal Articles
- 2012
[j1]Timothy N. Miller, Renji Thomas, Radu Teodorescu:
Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units. IEEE Comput. Archit. Lett. 11(2): 45-48 (2012)
Conference and Workshop Papers
- 2016
- [c7]Renji Thomas, Kristin Barber, Naser Sedaghati, Li Zhou, Radu Teodorescu:
Core tunneling: Variation-aware voltage noise mitigation in GPUs. HPCA 2016: 151-162 - [c6]Renji Thomas, Naser Sedaghati, Radu Teodorescu:
EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures. ISPASS 2016: 79-89 - [c5]Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin
, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas:
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. MICRO 2016: 54:1-54:12 - 2012
- [c4]Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu:
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips. HPCA 2012: 27-38 - [c3]Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu:
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors. ISCA 2012: 249-260 - 2011
- [c2]Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan:
StVEC: A Vector Instruction Extension for High Performance Stencil Computation. PACT 2011: 276-287 - 2010
- [c1]Timothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu:
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches. MICRO 2010: 351-362
Coauthor Index
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